1) An IO mapped eprom is hardly the same as a multi-master tristate bus but hey...
Nobody said a ROM is the same as a bus, or that it is IO mapped, the point is that it can co-exist.
2) The x86 Northbridge (or is that southbridge?) has like 2,000,000 gates or more to convert between buses and standards. Obviously I am not saying you would need even a fraction of those gates, but it is not going to be a sunday afternoons work.
I agree that it's not likely to happen, in an afternoon or otherwise. So maybe it's a pointless argument, but I disagree with your characterization that using some other CPU is substantially more complicated than existing accelerators. Dunno about the Duron, but I've looked at the socket 7 pinout before and the majority of pins are for power, debugging, and multiprocessor systems. The stuff that is relevant to interfacing the CPU to an Amiga bus is not really exotic.