"port" is probably the wrong word. Convert is more appropriate.
Not quite sure why you'd want to. Mixed VHDL and VERILOG works fine in sim & synthesis... I've got 10's of projects here with a mixture.
I guess it must be the developers preference. "Easier to maintain" probably means "Easier for me to read & change". Heh Verilog ain't that bad once you get used to it

As for support / updates for other targets... they could just take the new VHDL versions of the files no? As long as the partitioning / signals don't change (too much) the board specific stuff (usually in separate files) should still interface to the core. After all... MiniMig was only targeted for the MiniMig v1.1 PCB and people added BSP for different boards no problem.