Coldfire - Binary Compatible

[alexh]

I think the opcodes which are not the same are not commonly used in embedded systems which is where the coldfire is targetted.

They ARE binary compatible to a point, each of the affected opcodes can trigger an interrupt and run emulated routines.

[alexh]

Looking at the Fido thing, it's not 68k I/O compatible.

I wish that ematech guy would stop cutting and pasting all over the forums... a link would suffice.

[alexh]

eslapion wrote:
Anyways, with Tobias's TG68 and FPGAs getting better and better, soon we will be able to run a virtual 68060 at 250MHz or more using simple programmable logic chips.

Yeah right... NOT. Maybe in 10 years or so.

We can already run the 68000 at nearly 100MHz using cheap FPGAs.

They are hardly cheap, they still cost more (including an adapter PCB) than a real chip.

Due to the architecture, a 100MHz 68k would be lot slower than a 50MHz 060. Not to mention it doesn't have an MMU or FPU.

Add to that, Tobias's TG68, while a great achievment, is not 100% 68k compatible (yet).

[alexh]

Protek wrote:
Could an FPGA be used as a "middleman" with coldfire to handle the compatibility issues? In other words the FPGA would hold the logic to make instructions compatible in both directions in case an instruction was incompatible.

Nope that is not possible, for the same reason already given as to why you cannot replace these instructions in the binary file.

You do not know what is data and what is instructions (made worse if anything is compressed).

[alexh]

MASACREWILL wrote:
I wonder why they are not offering  Dragon and what is with ElBox anyway.. :roll:

I *think* it was a series of things:

1) The performance was not very good
2) The compatibility was not very good
3) They stopped making the exact coldfire chip that was on the Dragon.

[alexh]

The converter would have to RUN the code, and that just isnt possible. I doubt such a converter really exists.

[alexh]

rkauer wrote:
 My best shot: reverse engineering the 68060 and put the results in a FPGA, but clocked at a monster speed.

 Of course, this solution may be not very practical, because the cost of such FPGA (@least 400MHz, a dozen logic gates, BGA package and so on).

It's not practical because no single FPGA has the capacity for a 68060 or the ability to run at high speed with a design of that complexity.

The best solution for a new classic accelerator (or a faster MiniMig), is to find a source of reasonable priced rev6 060 chips. Either pulls from other equipment such as telecoms, or direct from freescale through sideband channels.

[alexh]

Krusher wrote:
With enough demand, an fpga can be made into an asic.

You're joking right? $70k NRE minimum

[alexh]

jarrody2k wrote:
I am saying it is possible, and dare I say, achievable by an experienced team of software engineers.

As an experience software (and hardware) engineer. I'm saying it isn't.