minimig 4000

[alexh]

I am sure that anyone who thinks they can make a profit supplying bare or ready bult boards will put in whatever money is needed.

There is no large scale profit, which is why no-one is mass producing MiniMigs.

I'll do it for £15k upfront, which will be paid back on first sign of a profit.

They still make both 040 and 060. I've bought E41J 060's before at €75 each. No-one will care about 040.

I know the 060 is 3.3v core voltage but I think it still has 5v I/O

Freescale  Data

SDR is still cheap and sold in very high quantities as it's in everything from DVD players to washing machines.

Personally I would prefer MegaMig. A MiniMig form factor with an 060.

[alexh]

FrenchShark wrote:
- A coldifre is less expensive than a 040/060 and you can achieve a 100% accurate emulation (not the illegal instruction hack) with an average of 20 CPU cycles per instructions.

Yeah right... NOT!

Emulation is good in a closed environment, as soon as you introduce external inputs, interrupts, exceptions etc. the house of cards comes tumbling down.

If it was possible and the speed was anywhere near a 50MHz 060 we'd have Dragon(?) boards by now.

[alexh]

A6000 wrote:
ECS is in the minimig FPGA which is used in place of the AGA chipset, it may be possible to reprogram this later to be AGA as I said in my earlier posts.

MiniMig is not ECS, it is currently a slightly buggy OCS. (Still great work though, a major achievement!)

[alexh]

HenryCase wrote:
An A500 wouldn't use the extra instructions of an 68060, right?

Wrong.

If the program is compiled for / written for 68060 it will use any extra instructions.

If not, a standard 680x0 program will use the improved architecture, parallel execution units, Instruction and data cache, branch prediction etc.

If all you want to do is run A500 software, stick with MiniMig.

Also bare in mind that a LOT of Amiga workbench software is written for 68020+ only.

HenryCase wrote:
If the main A500 clock runs at approximately 7.14MHz, we should be able to overclock the 'processor' part of the FPGA to high speeds for an Amiga CPU if we stick to multiples of this base value (121.38MHz, 164.22MHz, etc...).

It doesnt work like that.

Anyone know what the maximum clock speed for a Spartan-3 FPGA is?

Absolutely doesnt work like that.

FPGA's dont really have a "maximum clock speed". Their maximum speed is determined partly by type/generation of FPGA it is and mainly by the logic that is programmed into them.

While the FPGA might be rated to 300MHz, when programmed it wont do a fraction of that speed!

Maybe low 10's of MHz with a well written design. Certainly not 100's.

[alexh]

AeroMan wrote:
    I've talked with some friends who work with FPGAs, and they told me VHDL would fit best for this kind of project, althrough Verilog is easier to learn.

I dont know who you're mates are but they are either poor engineers or they make stuff up they dont know!

VHDL and Verilog are just languages, you can write exactly the same thing in both languages. They are equally supported in all Xilinx and Altera FPGA's tools and have been for a long time.

If anything VHDL got full support later than verilog due to it's extensive typing and features such as generate and records.

AeroMan wrote:
How many gates are we using from the Spartan ?

You should start thinking about SLICES and BLOCKRAM rather than gates. Gates is an ASIC metric. To know exactly how much MiniMig uses... try to Synthesis it. The Xilinx toolkit is available freely as is the MiniMig source.

http://www.amiga.org/forums/showthread.php?t=32604

AeroMan wrote:
I would like to know how big we could expect an AGA version to be...

Impossible metric to measure, even if you knew the current size of MiniMig. How long is a bit of string? You have no idea how much more complicated AGA is over OCS, or how well MiniMig is written or how well someone will write AGA.

AeroMan wrote:
The second one: wouldn't it be cheaper to use two or three smaller FPGAs for an AGA Minimig than upgrade to a bigger FPGA? The cost of those chips seems to grow exponentially.

Yes. Most designs (Prometheus, X-Surf, Mediator, Picasso IV) use multiple smaller FPGA's (CPLD's) rather than go to bigger ones. There is usually some cost / size boundary. However IMHO form-factor is a bit selling point of MiniMig. In fact to me, it's the only selling point.

[alexh]

AeroMan wrote:
I'm not stating that we should ignore what was done in Verilog and try to rewrite everything in VHDL. It was just one comment from them I would like to share.

Sure, but the comment is invalid.

AeroMan wrote:
Actually, one of them is PHD... What they told me in that discussion is that there are some stuff that you can implement in VHDL easier than in Verilog

Not true. Trust me I've worked as a Verilog and VHDL designer for over 10 years. Ask them to name something, just out of curiosity.

AeroMan wrote:
but it is more difficult to learn.

It depends. If you've never done C (software) then you'll find both equally difficult. If you've done any C then you'll probably favour verilog as its syntax is quite similar.

AeroMan wrote:
as Assembly and C are also languages and althrough C is very powerful, there are things that can't be done using it. You can do everything in Assembly, but it is way more difficult.

Nice simile. Unfortunately not a valid one. C is a high level language and Assembler is a low level language. VHDL and Verilog are both equally high level languages.

Verilog has pro's and cons, VHDL has pro's and cons. The majority are not valid for MiniMig as they centre on verification and code reuse.

AeroMan wrote:
With the 60% number that AJCopland said below, I can tell the hardware needs prevision for a second FPGA or a bigger one.

No you cant, cos you dont know how more complex AGA is over ECS. Dont try to tell me you do, cos you dont :-P

The only thing you could work out is if we had enough I/O for 32-bit CPU/RAM interface and 24-bit video interface.