JimS wrote:
how about an FPGA for logic and a byte-wide fast static RAM for each color..
That is the way most current scan doublers work. However they use a CPLD rather than an FPGA because the amount of logic you need is trivial.
JimS wrote:
if they make it in a 32-bit package, even better. It would make the board simpler, at the cost of wasting 8 bits/word.
This would make your FPGA/CPLD design more complicated but still feasible.
The problem means that you need write to the RAM at a rate of 27MHz while also reading from the RAM at a rate of 54MHz.
Previous implementations have opted for relatively expensive 3 * 8-bit dual port SRAM to overcome the reading and writing at the same time.
This is wasteful and poor design practice.
Instead if you make your rams 2x as wide and access two pixels at once you can read and write on alternate cycles.
Writing your own scandoubler is relatively easy. Writing your own flicker fixer is much harder.