Smaller, energy efficient turbo card for A1200

[alexh]

If you were to get an L88M mask version of MC68040RC40A it would be cool to the touch even without a heatsink and at the fastest 40MHz.

Much lower temperature compared to the "boil an egg" ones that were used in the Amiga.

[alexh]

bloodline wrote:
I'd probably use an XScale for this task, and run a 68k JIT emulator on it... or if I had some serious investment, then I'd probably use a Duron...

Like that would work... NOT.

What about the external BUS etc. hardware that you cannot emulate?

Before you know it you'd have almost created a 68000 CPU with glue logic just to get the square peg in the round hole!

[alexh]

bloodline wrote:
Well, since the alien Processor would be the bus master of the Amiga system, I would expect it wouldn't be to interface between the ZII and HT (for the Duron) bus's with an FPGA which could house a few other core's, like USB etc...

The HT to 680x0 bridge would be almost as complicated as a 680x0 processor. Not to go into too much detail here... it wouldnt work very well / at all.

[alexh]

I am surprised that no-one has considered making a 2nd generation 68060 accelerator using Rev6 silicon (which can go upto 100MHz) and SDRAM like the CT60 on the Atari Falcon

Given the current high price of CS-MKIII I bet a run of 100 could be profitable.

[alexh]

I have a two layer passive adapter board I made for CD32 that allows you to connect an A1200 trapdoor card.

The edge connectors are impossible to find ( or have a minimum order of 1000 ) which made it not feasible to release as a product.

[alexh]

It needs a particular 060 mask, or it won't run at that speed (labelled 68EC060, but actually contains the whole shebang).

Bollocks! The chips need to be what is called a Rev6. They can easily identified because they are prefixed with MC (MC68060) AND here is the important bit.... they have a MASK number E41J written in the corner.



The EC labelling has nothing to do with their speed capability. There are older MC68EC060 chips that cannot be clocked at 100MHz. The EC representation just means that the CPU was sold as a cheaper variant which is has a broken / untested MMU & FPU.

[alexh]

keropi wrote:
amigakit.com has new rev 060's...

Not officially.

The price for Rev6 68060's on ebay from my seller has almost doubled in the last 2 years. From 60 euro to over 90 euro.

[alexh]

Oli_hd wrote:
I would say KISS, 3.3V the CPU board, mount some SD-Ram on the board itself

You'd need an FPGA/CPLD for your 680x0 bus compatible SD-RAM controller. As there are non in existance (except the CT060) you'd have to design one or ask Rodolphe of Czuba tech if you can license his HDL source code.

Oli_hd wrote:
I think the overall cost of such a board would be low, except the 060

It is still too complicated for anyone not in the electronics industry. You yourself tried to do a Coldfire board several times and was never totally successful.
 
Even for someone who is in the electronics industry, regularly makes multilayer PCB's, can get good prices and understands the design constraints, producing volumes of less than 100 would still not be economically viable.

It is unfortunately a non starter :-(

[alexh]

Oli_hd wrote:
Actually there is [free SDRAM controller] I dont have the spec here at work but give me a couple of hours and I will be home.

There are free opensource SDRAM controllers, but it wont have a 680x0 bus interface. It will have AHB or wishbone or something.

Xilinx give away the VHDL code for use on Xilinx chips. (They have DDR ones too but on a 50Mhz bus thats pointless)

Doing a good quality 680x0 bridge will take some time. Czuba tech is very nice and has posted several FAQ's that will help but still it will take several weeks worth work (a few hours a day) to perfect.

Well you could use the Haynie archive PAL code from the 3640, stick it in a CPLD (using Abel) and then alter it. The full design is available, even though the 3640 wasnt the most pimped up CPU card ever made.

The A3640 is a CRAP card. It doesnt have a RAM interface and it doesnt support 68040 burst mode. Couple with that PALASM isnt the easiest thing to reverse engineer.

Is the PAL code available as source? Is it commented?

[alexh]

DamageX wrote:
I don't see where you get this idea that it will take "almost a 68000." Just look at any A500/A600/A1000/A2000 accelerator and you'll see that the 68000 state machine is at most a handful of oldschool programmable logic and TTL chips.

The logic on most Amiga accelerators is JUST a very simple 68k to DRAM bridge, plus some sort of asynchronous buffer from the higher speed 680x0 bus to the 7MHz Amiga bus. The two are VERY a like (and were designed to be so).

A non 68k bus to Amiga Bus will take a lot more glue logic, speed bridges, buffers etc. No one will ever attempt this. Too much work. No reward.

DamageX wrote:
A bus is a bus.

Spoken by a true non-technical user.

DamageX wrote:
Even a modern x86 CPU with hundreds of pins can still be interfaced with the slow 8-bit wide EEPROM that holds the BIOS.

1) An IO mapped eprom is hardly the same as a multi-master tristate bus but hey...

2) The x86 Northbridge (or is that southbridge?) has like 2,000,000 gates or more to convert between buses and standards. Obviously I am not saying you would need even a fraction of those gates, but it is not going to be a sunday afternoons work.

[alexh]

Interesting.

I found the Datasheet on the net, there is no real details about the interface timing. I suspect that it is not as good as Rodolphe's CT060 SDC. He went out of his way to maximise SDRAM performance for a 100MHz 060, taking advantage of any and all burst modes of the 060 processor.

The datasheet is also available here

If the part is still available through the reseller network it could reduce the cost of a 68060 turbo card considerably. A large gate FPGA could be replaced with a low gate count CPLD.