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Offline bloodline

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Re: Coldfire AGAIN
« Reply #14 on: March 29, 2008, 08:16:37 PM »
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HenryCase wrote:
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bloodline wrote:
How does this hardware know what is Code and what is Data? It can sit there as a parasite on the Data Bus, but it won't know what it's looking at...


Surely in 68k ASM the first "half" of code is the instruction and the second "half" of the code is the data? As the code would be of fixed length (16-bit? 32-bit?) the 'parasite' would know exactly where to look for an instruction, right?


Nope. Not the instruction format... the actual information traversing the Data bus, could be Code or Data... Only the CPU knows what the information actually is.

-Edit- And the 68k has variable length instructions... The parasite doesn't have a hope in hell's chance of ever correctly identifying the Code.

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Re: Coldfire AGAIN
« Reply #15 on: March 29, 2008, 08:26:05 PM »
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HenryCase wrote:
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bloodline wrote:
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HenryCase wrote:
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bloodline wrote:
How does this hardware know what is Code and what is Data? It can sit there as a parasite on the Data Bus, but it won't know what it's looking at...


Surely in 68k ASM the first "half" of code is the instruction and the second "half" of the code is the data? As the code would be of fixed length (16-bit? 32-bit?) the 'parasite' would know exactly where to look for an instruction, right?


Nope. Not the instruction format... the actual information traversing the Data bus, could be Code or Data... Only the CPU knows what the information actually is.


How does the CPU know what the information is? By knowing and following the instruction format, surely! :-D


Hmmm... this is going to turn into CPU 101... The CPU makes requests to the Memory, sometimes those requests will be for an instruction, sometimes those requests will be for Data (as requested by an instruction).

Since the CPU made the the request, it knows what will be delivered on the bus. Anything watching the bus won't know what is being transmitted.


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Re: Coldfire AGAIN
« Reply #16 on: March 29, 2008, 08:32:38 PM »
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biggun wrote:
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bloodline wrote:
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HenryCase wrote:
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bloodline wrote:
How does this hardware know what is Code and what is Data? It can sit there as a parasite on the Data Bus, but it won't know what it's looking at...


Surely in 68k ASM the first "half" of code is the instruction and the second "half" of the code is the data? As the code would be of fixed length (16-bit? 32-bit?) the 'parasite' would know exactly where to look for an instruction, right?


Nope. Not the instruction format... the actual information traversing the Data bus, could be Code or Data... Only the CPU knows what the information actually is.

-Edit- And the 68k has variable length instructions... The parasite doesn't have a hope in hell's chance of ever correctly identifying the Code.



The 68k "flags" instruction fetched on the debug pins. (Harvard Architecture).
So yes, you can from the outside distinguishe data from code fetched.


Does the Coldfire have MM capabilities of that scale?

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Saying that the idea of the paraside is not worth doing.

BTW, why did your claim that you are not allowed to change the Coldfire if you buy it?


You know full well that when you licence a core you don't buy the right to modify it. That was the reason why the Amiga Team chose the PA-RISC, because HP did allow the licensee of the Core to modify it.

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I think the real story is that you would not want to change it - as its too much work.


I stated that in my original post on the subject.

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The Coldfire is quite fast and powerful as it is.


We have yet to see proof of this!

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Re: Coldfire AGAIN
« Reply #17 on: March 29, 2008, 08:36:27 PM »
Ok... here is a CF emulator... lets see what it can do...

http://www.slicer.ca/coldfire/

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Re: Coldfire AGAIN
« Reply #18 on: March 29, 2008, 08:51:36 PM »
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HenryCase wrote:
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bloodline wrote:
Hmmm... this is going to turn into CPU 101...


I'm willing to learn. You never know, through my ignorance a good idea may emerge.


I used to think that... sadly, while ignorance used to allow abstract thinking, now is just causes you to fall into the same traps that people in the past have. It is always best to stand on the shoulders of giants :-)

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bloodline wrote:
The CPU makes requests to the Memory, sometimes those requests will be for an instruction, sometimes those requests will be for Data (as requested by an instruction).


Does the outgoing instruction know what it is requesting, or is it simply calling on a set memory space? Also, does memory get divided up into program space and data space or is it all jumbled up?


???

There is no outgoing instruction. At boot the CPU requests data from a predetermined (by the CPU manufacturer) location, this data will be the first instruction to be executed. Often this first instruction will be a jump instruction, that tells the CPU where to fetch the next instruction from. From there it's up to the system designer what happens... then next instruction could tell the CPU to move Data around the internal registers... or to add a register to a memory location or to copy the data from a location to a register... only the CPU knows :-)

Memory on the Amiga is jumbled up, Code and Data are all over the place... on a x86 it has an MMU that marks memory pages as Code or Data... but then  you would still have the problem of variable length instructions.

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Re: Coldfire AGAIN
« Reply #19 on: March 29, 2008, 09:22:48 PM »
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HenryCase wrote:
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bloodline wrote:
???

There is no outgoing instruction.


I worded that badly, I should have used 'outgoing signal' instead. What I'm trying to get at is does the CPU give clues about what it is trying to fetch?

If not outgoing signals then are there CPU pins you can monitor to get information on what the CPU wants to do with the information it gets next?


The CPU is not required to let anyone else on the bus know what it is trying to fetch. systems with an MMU (and as Biggun states Harvard Architecture) do provide signals to let other bus users know what's going on, this is useful for multiCPU systems where caches need to be kept coherent. The x86 provides this sort of data...

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bloodline wrote:
Memory on the Amiga is jumbled up, Code and Data are all over the place... on a x86 it has an MMU that marks memory pages as Code or Data... but then  you would still have the problem of variable length instructions.


Is the variable length instructions issue not something we can work around? Let's say the 'parasite' is looking for the instruction 0x000189. Whenever this code comes up the 'parasite' looks at the code following it. If it follows the format it is expecting then it tries to use it, if not then it lets the CPU try to handle it.


The problem here is that you would need to simulate the entire frontend of the CPU to follow what's going on... and even then, exceptions and interrupts will throw the whole thing out... I hope now you can see how difficult this idea would be!

Don't forget that an instruction is just a number, that number means something to the CPU, but only the CPU knows if that number is telling the CPU what to do next, or if the CPU needs that number for a calculation.

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Re: Coldfire AGAIN
« Reply #20 on: March 29, 2008, 09:49:06 PM »
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HenryCase wrote:
@bloodline

Well I'm convinced enough that the 'parasite' idea isn't worth pursuing now, little more difficult than I had hoped. Thanks for your help bloodline.


No worries, CPU design is a fun topic... I should say, was a fun topic... it's all very complex now... the Amiga was the last of the understandable architectures... now you need teams of people.

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Coldfire still shows promise IMO. Maybe we could do a bit of research into 68k-Coldfire compatibility. This should be a good place to start looking:
http://tinyurl.com/3exnxn


Well, the V4 and V5 cores, with their separate supervisor stack do seem to have what it takes to emulate the 68000 (not sure about the data width issues though)... but the instruction traps which will be required are very expensive in terms of CPU cycles... I really do think we are looking at a massive penalty with the coldfire... until I see one in action I can't be 100% sure, but from what I've read I'm not hopeful.

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Oli-HD please contribute to this discussion, your input will be very valuable here.


Indeed...

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Re: Coldfire AGAIN
« Reply #21 on: March 29, 2008, 10:36:33 PM »
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minator wrote:
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You know full well that when you licence a core you don't buy the right to modify it.


That will depend on the exact terms of the license.  These aren't exactly shrink wrap licenses, probably specific to each licensee.

e.g. DEC, the designers of StrongARM had an ARM architectural license, that allowed them to design their own processor from scratch.


But for the tiny sums of money (and low production runs) we are talking about, there is no way Freescale would allow any modification to the core.

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Re: Coldfire AGAIN
« Reply #22 on: March 29, 2008, 10:45:34 PM »
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HenryCase wrote:
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bloodline wrote:
But for the tiny sums of money (and low production runs) we are talking about, there is no way Freescale would allow any modification to the core.


Why would money/low production runs come into it? If the redesign work was done by a 3rd party, and the cost of manufacture was the same, where would Freescale be losing out?


That has nothing to do with it, it's about access to the technology. The less you pay the less you are allowed to do with the IP.

-Edit- missing word :-) oops too late :lol:

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Re: Coldfire AGAIN
« Reply #23 on: March 30, 2008, 12:14:26 AM »
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A6000 wrote:
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bloodline wrote:
Well, the V4 and V5 cores, with their separate supervisor stack do seem to have what it takes to emulate the 68000 (not sure about the data width issues though)... but the instruction traps which will be required are very expensive in terms of CPU cycles... I really do think we are looking at a massive penalty with the coldfire.


As I understand it, the coldfire is cheap, that is really the only thing it has going for it.


hmmm, it's not that cheap...

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The amiga is a multitasking computer, so why not use 2 coldfires, running separate tasks, while one chip is trapping and emulating code, the other coldfire continues running it's task, hiding the speed penalty that emulation brings.
A few extentions to kickstart (in ram) will enable the OS to use 2 processors simultaneously.


Not  chance of Exec supporting 2 CPUs (this would require a complete rewrite, and Memory protection would help). Michal Schulz  and NicJA did some work on getting AROS's Exec SMP ready, but... that was for x86 CPUs which are built for SMP (with extremely powerful MMUs and extensive cache coherency hardware).

Other than that, most Amiga programs spend their time sleeping, so it wouldn't really offer much improvement...

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Re: Coldfire AGAIN
« Reply #24 on: March 30, 2008, 02:42:45 AM »
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JetRacer wrote:
If I recall correct, the 060 is 32-bit pure and hardware emulates <32-bit by simply stripping the communication since it would take more resources to do it "the right way" (and it wouldn't shave any cycles anyway). As others pointed out: modifying CF to do this is not a viable option. So (finally) my question is: will doing this with JIT have a notable impact on performance?

By "notable" I don't mean a reduction of a vanishing factor 4 in the scope of a x1400 or x140 gain.


A JIT shouldn't cause too much of a performance problem, it is the best solution really... the big question is if we are using a JIT, then why bother with a Coldfire, when you could use any CPU... a cheaper more powerful one...

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Re: Coldfire AGAIN
« Reply #25 on: March 30, 2008, 05:30:58 PM »
@Biggun

I totally agree with your criteria for choosing the Coldfire in your last post, since you are not looking at it as a derivative of the 68k... but my argument revolves around the fact that we should be looking at all the available CPUs which can be licensed for use in the NatAmi project, and not just select the Coldfire because of it's history.

MIPS and ARM provide all the same services as Freescale, but with the advantage that both of those architectures are more widely used and better supported. Also, in the case of the MIPS, its implementations are tiny!

If the V4 and V5 versions do offer a very high degree of compatibility with the 68k and require only minimal work to support the existing Amiga software base, then and only then does the Coldfire have an advantage over the MIPS and ARM. Otherwise it's probably not the best choice, since the same amount of work would be required to get it to work regardless of the CPU architecture used.

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Re: Coldfire AGAIN
« Reply #26 on: March 30, 2008, 05:43:22 PM »
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Karlos wrote:
I know, let's use PowerPC...

*hides*


Actually, in this case... If it fit the criteria, I'd agree! :-D

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Re: Coldfire AGAIN
« Reply #27 on: March 30, 2008, 09:09:28 PM »
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Karlos wrote:
It has the advantage that it could run the PPC descendants of AmigaOS too...


Hmmm, it does... perhaps an embedded PPC would be right for this application... no wait, Karlos, you are not going to get me to endorse the PPC! ;-)  :lol:

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Re: Coldfire AGAIN
« Reply #28 on: March 31, 2008, 01:58:05 PM »
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HenryCase wrote:

I am currently investigating how easy it will be to add full memory protection to AROS (without throwing away AmigaOS 3.1 API compatibility),


The answer is: Not very. i.e. Impossible. While the exec design team clearly envisiaged memory protection at some future time... none of the rest of the OS design team did (I think intuition alone is a very bad boy!), and public/private memory flags were never enforced.

Tasks and libraries happily pass memory pointers around without a care in the world.

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Re: Coldfire AGAIN
« Reply #29 from previous page: March 31, 2008, 05:58:57 PM »
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HenryCase wrote:
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bloodline wrote:
The answer is: Not very. i.e. Impossible. While the exec design team clearly envisiaged memory protection at some future time... none of the rest of the OS design team did (I think intuition alone is a very bad boy!), and public/private memory flags were never enforced.

Tasks and libraries happily pass memory pointers around without a care in the world.


That is useful information to me bloodline, so thank you for that. None of what you describe makes retrofitting memory protection impossible though.


It does if you want all your old software and large parts of the OS to keep working... :-D

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Let me explain...


:nervous:

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The memory doesn't have to flag whether it is public or private as long as the API functions asking for memory space are not allowed direct access to the memory.


When you request memory from exec you are supposed to flag the memory if it is to shared or private. Although in AmigaOS this actually does nothing (due to the early machines not having an MMU), this tells the OS that the memory should be allocated in either the task's private address space or if it should be allocated in some public memory pool (where anyone can mess around).

Due to the lack of MMU, these flags were never enforced so no amiga software actually bothers to set them properly... Enforcing them nnow after 20 years would break a lot of apps.

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You put an OS layer inbetween memory allocation functions and the real memory. This MMU gives the memory allocation functions the impression that it is writing directly to the memory, when in reality it is controlling memory allocation/deallocation and protecting unwanted memory access.


I don't understand... The way memory protection would work is that each task gets it's own address space... in effect each task gets up to 4gig of address space to itself. I shall expalin the reprocussions of this later...

A good book on how MMU's work should give you a better understanding... The intel developer docs are a great place to start!

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For those memory functions called without a flag, the memory status is set to private by default.


Well that would break EVERY app, since it is the exact opposite of the current situation... for there to be any hope of this working at all... the default behaviour needs to be the same as current behaviour.

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You then have the issue of inter-program communication. For this, you want to allow the programs to attempt communication, but you want to prevent incorrect values being entered into the program space and potentially crashing the OS. You allow the value to be passed by the first program, but the MMU checks to see if the value is valid before it passing it on to the second program.


One of the great things about AmigaOS is that is places no restrictons on what is passed in an exec message... In effect the OS has no idea what the programs are sending to each other. (it's the same problem as the parasite emulator we discussed before).

Now here is where the problems begin... You have two tasks, both have their own address spaces... one task sends a pointer to a data block to another task in a message... that pointer is meaningless to the receiving task, since the pointer is either not vaild in its address space or pointer for somthing completely different!

The only way around this is to have a public pool of memory mapped to the same address window in all task address spaces... but since the public/private flags were ignored this can't work.

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For the few programs where this method is not suitable (where you need as much speed as possible for example) the MMU can either be switched off or the program can be patched. The MMU will only be known to the new kernel and the user, the API functions will not be aware of its existence, so they will not mind using non memory protected mode.


You can't just switch off the MMU once it is on... the whole integrity of the memory structure is maintained by this device... Switching it off would leave the memory in effectly a random jumble of 4k blocks that used to mean something...

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Those are my ideas as they stand at the moment. As I said I am still conducting research into the feasibility of a memory protected AROS.

Do you think my ideas are sound in principal?


Not really :-)

MMU's are hard to get your head around at first but some solid study and a lot of running it out on paper with a pencil will give you a good idea of the issues here...