eslapion wrote:
bloodline wrote:
The 060 was something like 1 and a half million gates... you can't get an FPGA big enough yet... AFAIK.
The Core2 Duo is something like 250million gates...
The Virtex 5 family can offer up to 330'000 gates. However, it can run up to 550MHz. Also, nowadays DDR2 memory can run so fast that there is no point in giving any cache to a virtual emulated processor in an FPGA.
How many gates would the DDR2 controler use? 30% at least... doesn't leave much left over...
Therefore, I suppose, it might be possible to reproduce something that would be cacheless but whose performance would be "like" something halfway between a 68030 and a 68040 but whose whole RAM is the cache.
Hmmm... my 50Mhz 030 gets about 10MIPS... my 25Mhz 040 gets about 20MIPs...
Getting an FPGA emualtion of the 68k working without any cache, at anything like 15MIPS would be a real challenge...
If you had a 550MHz emulated 68k processor whose RAM is actually just as fast as the cache then I can't think of any way an emulated CPU could be as fast. Unless you buy yourself a quad core running at blazing speeds. However, right now, WinUAE still appears as a single thread.
It doesn't work like that... Cache is low latency... RAM is high latency.
In order to run faster, WinUAE would have to become multithreaded to use multiple CPUs. Assuming you can actually gain any speed by doing so.
You could get the JIT to emulate a dual core 68k... that would require SMP support in the 68k OS though.
The FPGA is designed for flexibility, not speed. Central Processing units are massive and complex devices... that is why it takes massive companies with huge budgets to develop them.
Modern processors are not developped with emulation in mind. They cost billions to develop because they can run their OWN code at dazzling speed. That's not what we want to do here.
what is emualtion... how is it different from what a CPU normally does...?
JIT maps 68k instructions to x86 instructions... The 68k program is actaully turned into an x86 program... no interpetation is required... registers permitting, it would be close to 1:1 (though I imagine it would be 1:2 on average) .. the CPU is unaware that it's running a program written for a different CPU.
The bottom line is, can a programmable logic system emulate the 68k processor faster than the real thing was and at a lower cost than a x86 PC ? I think so.
Time and equipment cost... not to mention testing would be far greater for the FPGA... that's why there are no FPGA emuations of any CPU more complex than the 6502...
If somebody can program a JIT emulation for a piece of software then I am convinced it is also possible to do it for programmable logic.
Of course it can be done... but this situation is best suited to a JIT than to an FPGA.
