A500 DRAM timing diagrams

[Zac67]

Agnus' DRAM interface isn't suitable for SRAMs which have no multiplexed address bus. SRAMs can rather easily be interfaced to the CPU bus directly as FastRAM - just generate a CS and you're probably good to go.

[Zac67]

Of course it's possible. You just latch the high address part on _RAS and then use _CAS as _CS (more or less, there may be some tweaking required). But what's the point? It's easier to add it to the CPU side and faster as well.

SRAM doesn't require any refresh btw (and can't make any use of the cycle).