OCS discussion

[Zac67]

IIRC, 4-plane 640px takes all the video bandwidth on OCS.

Actually, 4-plane Hires takes all the chip RAM bandwidth there is. (Excluding horizontal and vertical blanking times that is, but with severe overscan there's not too much left.)
8-plane Lores could bandwidth-wise be possible but there are no such modes.

[Zac67]

It's my understanding AGA can handle HAM in super high res, but then isn't HAM emulated and not really the same technology in AGA?

HAM6 isn't emulated, it's still native to AGA. In addition to OCS/ECS's HAM6, AGA introduced HAM8 - 2^6=64 color palette or 6 bits of R/G/B variance. Since AGA quadruples video bandwidth (double clock & double width) it can run 8 bitplanes (planar or HAM8) even in SuperHires.

Do accelerators remove this memory bandwidth contention or do they sit on top of it?

Accelerators have no impact whatsoever on graphics capabilities, chip RAM bandwidth and such. For that you'll need to head the RTG route.

[Zac67]

(double post, sorry)

[Zac67]

The A501 expansion RAM and Zorro-II RAM all becomes slow-RAM in an A500 ..?

No.

With the original A500 Agnus you'd get the infamous 'slow RAM' at $C00000. This happens because the PLCC Agnus was expanded to allow for addressing of 1 MB (much cheaper than an extra RAM controller), but C= 'forgot' to upgrade the chipset registers with the neccessary address bit, so the chips themselves can't reach that high. To make sure that the RAM isn't configured as chip RAM (which simply wouldn't work) the highest address bit is swapped so the RAM appears at $C0 instead of $08.

Since the 'slow' RAM is accessed through Agnus and the chip bus, the CPU has to wait for the bus to be available - thus it isn't any faster than real chip RAM.

For ECS they made up their minds and added the missing address bit to the registers and voilá - 1 MB chip RAM were there.

The A3000's chip RAM is slightly different (similar to AGA) as the CPU can access it 32-bit wide - effectively the CPU's getting double bandwidth. It's no real surprise that Alice is somewhat pin-compatible to the A3k's Agnus and with AGA the 32 bit access can be used by video DMA as well.

However, the CPU's got its own bus with ROMs, CIAs - and fast RAM. This is usually Zorro II connected and it's never slowed down by the chipset!

[Zac67]

@freqmax

An A501 is nothing more than some RAM chips, a battery and a clock chip. Since it's also limited to 512 KB there's not too much point in trying to adapt it to Z II.

I know this doesn't matter, but I'd like to understand what you mean.  Why would a control shift not look nice in high res if you have four index colours?  You simply shift away as needed.  You have the ability to change the value of any of the rgbs per control so you could set an index on pixel one and the rest of the image could be a control in theory.

The image I produced assumed 2 colours index (is it really 4?) and uses control RGB changes for each adjacent pixel.  Looks pretty bloody nice to me.

A theoretical HAM4 mode would require 2 bits for mode control: 00 = use index palette color; 01 = hold GB, modify R; 02 = hold RB, modify G, 03 = hold RG, modify B. With the 2 bits left you'd be able to use 4 palette colors. In contrast to HAM6 where the modify value is 4 bits, i.e. you can change any of three subpixel full range, you'd only have 2 bits for modify as well. How'd you want to use them? Step up / down 1 or 2 little steps?