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Author Topic: A500+ Rev 8a mobo IDE I/F?  (Read 1452 times)

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Offline Zac67

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Re: A500+ Rev 8a mobo IDE I/F?
« on: August 07, 2007, 05:54:15 PM »
Found it in the SM (page 5-7), no idea if this is for a HDD interface...
_OVR is "override system decoding" (switches off Gary's CS outputs)
_XRDY is "external data ready"

Does make sense in a way to build an IDE I/F on top of that, but most is still missing (access to data & address bus, CS generation, latches - the busses aren't even available at Gary's socket). The only sense it'd make is to supply missing signals to an IDE adapter in the CPU socket, in order to avoid ugly (and error prone) 'flying' wires on the board.  :-?