8 Mb CHIP RAM on All Amigas

[Zac67]

@Tricky: There's no point in using a MMU for the chipset (not the normal, CPU integrated one of course, but one you build for that purpose).

1) An MMU can help mapping logical memory to physical memory - provided the address space of logical memory is larger than the amount of physical memory, so when a currently not existing page is accessed, you stop access, load the contents to physical RAM and then map it to where you need it. The Amiga's chip mem address space is equal to the physical RAM (2MB), so there's no sense in that.
2) If a page miss occurs, you need to stop access (using an exception) for loading the data to RAM. So how do you do that while the frame is displayed or the sound is played?
3) Chip RAM access by the chipset is realtime, that's the whole point of creating chip RAM in the first place: define memory that can be accessed in a defined manner. The CPU is stalled when the chips need the bus. Fast RAM on the other hand can be accessed by the CPU without being slowed by chip access.

[Zac67]

OK, but
- How does the OS now which part of code owns which parts of chipram? What happens if the user drags a screen?
- Chip registers ARE being written to be chips (i.e. by Copper). No big deal when it comes to color registers, but what about Copper controlled blits? Of course you could use the MMU to supervise access to the 'virtual' registers, but then again you'd have to emulate chipset behavior...

Apart from that I don't like the idea of [d]paging[/d] banking chipmem very much, sorry. I'd rather use an RTG card for graphics and a DMA capable sound card. What else would you need chipram for? The whole scheme was engineered for a highly efficient, low cost, yet high performance graphics machine. Technology has moved on since.

[Zac67]

Sigh...

Look, any chipmem access by the chipset works like this:
- Agnus generates the address to the chip bus (for the 'DMA')
- the data gets transferred to the chip that needs it

All address registers for the custom chips reside within Agnus (hence its name from Address Generator). The registers are 21 bits wide and the address bus is 21 bits wide (not precisely since we address words/longwords, but that doesn't make a difference).
There's absolutely no way to make Agnus see more than 2 Megs - apart from redesigning it of course. A redesign would need
- additional address lines to CPU bus switch
- additional address or select lines for RAM control
- enlarged address registers
- additional or larger RAM chips

The whole idea about virtualising chipmem and swapping it when needed won't work, it leads to the exact same problems there are with resource tracking within AmigaOS - there's simply no way.
And: Before you engineer a special MMU for the chipset, it'd be much simpler and more efficient to redesign Agnus (wouldn't need a major OS rewrite). So, go ahead and ask Dennis to share his Minimig work with you to build a (nearly) drop in replacement for Agnus.

[Zac67]

I really didn't want to do this, but I just checked the A4k schematics to make sure I'm not telling crap.

- Alice is actually connected to all 32 address bits - this surprises me
- Alice has 10 DRAM address bits, 11 with the '8 MB' jumper set - that's enough for 8 MB (no surprise here)
- Paula just has a register address bus of 8 bits, no data address lines
- Lisa likewise

Like in OCS/ECS there's no bus arbitration for the chips. Alice knows who wants what and uses the static (prioritized) 'DMA channel' scheme to ensure timely data delivery. It generates the addresses and Lisa/Paula read the data.

It was possible to expand a 1st generation A500 to 2 MB chipmem by exchanging Agnus, and the A4k schematics talk about a '8 MB Alice'. I see no reason why you'd need anything more than a new (non-existant) Alice and RAM.

[Zac67]

Read my post - max amount of chipmem depends on Agnus/Alice and nothing else.
AmigaOS doesn't really care how much chipmem there is and where - it detects the first 2 MB as chipmem and additional RAM can very easily be flagged MEMF_CHIP.

[Zac67]

Yeah, Dave tried that in the early 90s: AAA

[Zac67]

Imagine having 256 Megs of DDR2 Chipmem.
Imagine running a 68080 @ 2000 MHz.
Imagine an Amiga Two - 64 bit architecture, of course.
Imagine AmigaOS 5.0.

Dream on. :roll: Some things just don't happen out of thin air.

[Zac67]

@Piru
What's the problem with Denise/Lisa? Don't they just take what they're given by Agnus/Alice?

[Zac67]

 :bow:

One thing confuses me though: in the A4k, Alice has the complete address bus connected, so in theory you would 'only' need to
- redesign Alice for larger registers
- the 11 DRAM bus lines should be enough for 8 MB
- put in an 8 MB PS/2
and off you go (apart from OS/Zorro issues).