Enter the Dragon or enter the vapor?

[MskoDestny]

eslapion wrote:
Its NOT needed in the V4e core!!!

All previous cores needed that but not on the V4e!!!

Well, yes and no. The V4e solves most of the bigger compatability problems, but it's not perfect. There are a couple of multiplication instructions that set flags on 680X0 chips but don't on ColdFire and the floating point format isn't compatible (80-bit vs 64-bit IIRC). Plus there are still a bunch of instructions that aren't implemented on the V4e so you either need to emulate those instructions by trapping exceptions (as the library supplied by Freescale does) or write a dynarec/JIT that translates the offending instructions before executing them.

[MskoDestny]

Donar wrote:

Lemmink wrote:
... but the Elbox coldfire will never go faster then any 68060 accelerator for the Amiga. The outcome of the presentation was that the card ran unmodified / optimised software at the speed of an 68040 at about 33 MHz. ..

The thing that i do not understand is: The Coldfire is (Mips wise) roughly 4 times faster than a 68060 @ 70 MHz it shares a good lot of instructions/adressing modes with the 68k (75%?). Why shouldn't it reach the performance of an  68060 or more?  :-?

Exceptions are rather expensive on modern pipelined processors as the pipeline has to be flushed. The V4e has 9 pipeline stages so each time it hits an unimplemented instruction it burns through 9 cycles before the first instruction that emulates the missing one finished completion and it is going to need to execute several instructions to simulate the missing one. The 68060 can execute >1 instruction per cycle on average (note that it takes longer than 1 cycle for an instruction to complete because of pipelining, but more than one instruction is inflight at a time). So it probably takes a ColdFire CPU upwards of 10 cycles to execute certain instructions that might have taken effectively 1 cycle or less on the 060, but the ColdFire is only clocked about 4 times as fast.

A well written dynarec should have a much lower performance penalty, but it's much harder to write than a trap based solution.

[MskoDestny]

A dynarec/JIT doesn't really have to be all that slow. You don't have to deal with the mess of emulating a fundamentally different architecture, just expanding certain unimplemented instructions into multiple implemented ones. You don't have to deal with register mapping or simulating flag behavior (well except for those previously mentioned multiply instructions). Plus in theory, a sufficiently advanced dynarec can actually improve performance. HP's Dynamo is a dynarec that doesn't do any translation between architectures it just does processor specific optimizations and optimizations that can only be reasoned about at runtime.

[MskoDestny]

@Karlos:
Your posts are the only reason I know about HP's Dynamo. I just couldn't remember who had brought it up.

Oli_hd wrote:
Wouldnt help Im afraid, my problem was with the coldfire/68K bus interface with the V4 CF.

Out of curiousity, what in particular about the MCF5407 bus was the problem?

A V4e CF card may work, assuming you used the PCI bus of the CF as the interface between the CF and the miggy while keeping all address mapped correctly.

Too bad the 5407 is the only V4 or V4e Coldfire that isn't in the hobbyist unfriendly BGA package.

freescale have put up a "Make your own Coldfire" proggy which you build from the basic blocks and when the design is done it gets e-mailed to Freescale... what happens then I dunno, if enough people want the same thing maybe it gets made)

I would guess it's for high volume customers that are ordering in the kind of quantities that make a custom manufactured part practical. I could be wrong though.