Some interesting Altivec figures

[KennyR]

Dunno if people are aware of this already, but... Wanna see how powerful Altivec is?

RC5 isn't a general benchmark, let's get that straight first off. It's not even a particularly useful one. It takes no account of system speed, and only uses raw number-crunching abilities of the CPU and its internal cache and registers.

But anyway, my Pegasos G3/600 can do around 2 million keys per second. My Athlon 1.3GHz PC can do around 4 million. Pentiums are considerably weaker, and maybe more modern Athlons are too.

But from what I've heard, Pegasos-2 G4/1GHz using the Altivec core can manage 10 million keys per second. Presumably an AmigaONE/G4 can do the same. G4 Macs certainly can.

Note that this is not an open invitation for another boring x86 vs PPC thread (since this info has little practicality in everyday use), and I just thought people would be interested in seeing the power of Altivec, when used for what it was really designed for - raw maths.

[KennyR]

More precise benchmarks.

[KennyR]

Problem with more modern x86 is that they removed an instruction used by rc5, to streamline the core, or so I'm told - I don't know much about it. So Athlon64 wouldn't necessarily mean faster rc5 cracking, although it would beat the proverbial crap out of G4 every other way.

Isn't there an Athlon64 listed in that 2nd url I gave, too? Is it the same one you mean? If so it's about 6 million keys at 1.6GHz.

Anyway, happy new year, and what the hell happened to your boings and Rank?!?! :-o

I trancended. Happy new year, mortal. :-D

[KennyR]

@Aragorn

That's OGR nodes. We're talking RC5-72 keys.

Edit: though it doesn't matter, sorry. I didn't see you were comparing different CPUs fairly.

[KennyR]

Hammer wrote:
RC5 is not the only benchmark to test for raw number-crunching abilities of the CPU and its internal cache and registers.

Why not OpenSSL benchmarks (it should fit within full size L2 cache)?

This isn't really an exercise to prove any magical superiority of PPC over x86, simply to show how powerful Altivec was in its element. RC5 just happened to be around. As Dr_Bombcrater said, it just happens to depend on how good the CPU core is for certain instructions. Thats why x86 are relatively weak at RC5 - they had many normally obscure instructions like those used for rc5 removed for better overall speed.

Oh, and isn't L2 cache external? Seems to me you can get a lot more number-crunching speed by not using external cache at all, and I think the RC5 core does fit in L1.

Anyway...

Since you know a lot about CPUs, can you answer this - why was an equivalent of Altivec not implemented in x86 cores? Was it a marketing issue (with Altivec speed boost being 'invisible' to consumers, and higher clock speed being very visible)? Was it not possible to implement? Or was it just useless?

[KennyR]

Bloodline wrote:
It is implemented in x86 CPUs, it's called MMX, MMX2, 3DNow!, SSE, and SSE2...

Boo, they were marketing gimmicks that only slowed the CPU down by adding more instructions to increase the instruction decode time per cycle. Their effect was negligible. Altivec's obviously isn't.