I don't know of any processor that supports breaking for an interrupt mid-instruction - that would be overly complex to implement, introduce a highly undesirable degree of non-determinacy, and not get you anything more than slightly lower interrupt latency for the trouble.
Doing it for an interrupt is unnecessary, but a 68010 or above will stop mid-instruction, save the processor state on the stack, and allow you to resume the failed instruction on a bus error.
