Minimig PCB run - interest thread

[mongo]

The XC3S400-4PQG208C alone is about $22 in 100+ quantities.

[mongo]

Switching from the Spartan 3 XC3S400 to a Spartan 3E XC3S500E would give you about 17 extra I/O pins while still keeping the 208 pin package. It would also give you a good bit of space for bug fixes and/or future enhancements. The current Minimig design uses up about 82% of the XC3S400, but only 65% of an XC3S500E.

Personally, I'd like to see a real floppy controller, IDE controller, a Kickstart ROM socket and possibly a Zorro-II slot added to the Minimig.

There is also an open source Atari ST clone. It would be nice if one board could be used for both the Minimig and the ST.

[mongo]

Baby steps folks. Nevermind the PCI and IDE and all that crap. If future expansion is in our minds, we should focus on Zorro-II and possible RAM/CPU expansions first. Zorro-II being the first priority, as there are many A2K expansions out there (like SCSI interfaces) that would be well within the realm of MiniMigs current specs.

IDE would be cheap and easy to add. Really not much point in using a Zorro-II SCSI card.

Zorro-II would be easy to add too, since it's pretty much just the 68k bus with a few extra signals added.

I wouldn't bother with PCI though, too much hassle and too little gain. Especially since the Minimig is currently 68000 only.

16 bit sound and RTG compatible video cards could be integrated within the FPGA itself, no need to use an external device for these.

[mongo]

Alternately you could connect the Zorro bus bridge directly to the CPU bus, leaving the FPGA to do the rest of the chipset. Using a serial link to another FPGA (or even a CPLD) would be fine for slower peripherals such as IDE.

The Zorro bus IS the CPU bus.

Same deal with the IDE, for the most part.

[mongo]

Given a machine as Minimig what would you use an IDE drive for? At least when against a 2Gb USB pen, where you could fit almost any games and change it on the fly and cheaply.

USB requires a USB controller and a USB stack, both of which are more complex to implement than IDE.

Besides, Compact Flash cards work quite nicely on IDE. No need for a hard drive if you don't want one.

[mongo]

For a 2layer PCB, you did a nice job on the layout and helped to keep the blank pcb very affordable.

For small quantities, a 2 layer board is much cheaper, but for large quantities (100+) a 4 layer board isn't that much more expensive.

[mongo]

Talking about that (and I don't mean to sound ungrateful) I would have thought Composite/S-Video would have been a necessity on this thing, considering how console-esque it is.

An Analog Devices AD723 could be used to generate both Composite and S-Video output from the MiniMig's RGB.

Probably add about $6-7 to the cost of things.

[mongo]

narmi wrote:
Adding composite/s-video output would take up precious board space.  You need several components in addition to the encoder chip, including some large electrolytic capacitors, and possibly one or two clock sources.

The AD723 does not require output capacitors and the clock can be supplied by the FPGA.

[mongo]

JimS wrote:

As to IDE support... has anyone considered SATA? It needs fewer pins.

The FPGA in the MiniMig currently has 4 unused I/O pins. That's more than enough to add IDE.

[mongo]

Unless you can find or write a 68K core that can fit in the XC3S400 currently used by the MiniMig there is very little point.

To use Wolfgang's 68K core, you would need a much bigger FPGA.

Not much point replacing a $7 CPU when you need an FPGA that costs $20+ more to do it.

[mongo]

jkonstan wrote:

1. The lack of more FPGA pins (soldering hobby/home project limit of 208 pin QFP on FPGA). The new extra FPGA pins could be used for IDE, Compact FLASH, parallel interface to Vinculum VNC1L (USB host controller with a CPU core and USB stack),  etc ....

2. The 68K bus clock rate limit on a two layer PCB. A larger Xilinx FPGA (more CLBs) with a soft 68K core embedded in it could possibly clock the soft 68K faster than the external 68SEC000. This would have to be investigated by compiling Wolfgang's VHDL code and running Xilinx timing analyser on it.

   :-)

There are enough free pins on the FPGA to do IDE as it is with a few external components and Compact Flash can also be connected via the IDE port.

Wolfgang's 68K core will run up to about 17 MHz in a Spartan 3.

The easiest was to gain more I/O pins is to change to a Spartan 3E. The design changes are minimal, you can still use the same 208 pin QFP package, and you gain more gates and more I/O pins.

[mongo]

jkonstan wrote:


I agree that Spartan3E is better way to go on an update to MiniMIG.

I have implemented several IDE interface in Verilog over the years; thus, I am pretty curious. There are 4 spare FPGA spare I/O pins left in MiniMIG1. How do you intend to support/implement an IDE interface (IDE_RESET, CS0*, CS1*, INTRQ, DMREQ, DMACK, IORDY, IORD*, IOWR*, ICS16*, DASP*, DA0-DA2, DB0-DB15) which require at least 12 FPGA I/O pins and some external CBT16245 level shifters used on 68K bus ?

Address and Data lines connect to the 68K via level shifters, same with the Reset line. IORD*, IOWR* CS0*, and CS1* can easily be generated completely externally, though you can reduce the number of external components if you use one output line of the FPGA as a IDE Chip Select line. IORDY has to go to the FPGA for it to generate wait states for the 68K if needed, but even that might not be totally necessary unless you plan on using a really old drive. INTRQ has to go to the FPGA, unless you want to poll the drive instead of using interrupts, but I don't recommend doing that if you don't have to.

DMARQ, DMACK, ICS16*, and DASP* aren't needed.

3 FPGA I/O pins and a few external components are all that are required.

[mongo]

jkonstan wrote:

Your description shows that you need more than the 4 programmable FPGA Spare I/O pins that are left on MiniMIG Ver1.0 J9 header in order to build the IDE interface that you described and that the MiniMIG PCB would need a new PCB layout. Of course if you add a CPLD/external logic and a bunch of level shifters to MiniMIG, a PIO mode IDE interface could be built.

I need 3 I/O pins and a little external logic to implement an A600/A1200 compatible IDE port, which would allow booting from an IDE hard drive with an appropriate A600 ROM.

I could do it with 2 pins, if I really wanted to.

A new PCB layout is a given if you are going to add IDE.

PI/O IDE is ok; however, DMA can be nice when one can DMA directly into SRAM. Thus, I would not write off the need for DMAREQ and DMACK.

Sure DMA is nice, but it's really not necessary. It also requires new drivers and a separate bus for the IDE, unless you want to shut off the 68K during DMA transfers.

IORDY for IDE would be nice when some users trys to hook there old small IDE hardrives from their old Amigas onto a MiniMIG at some point.

  :-)

I don't have a problem with that. You still don't need more than 3 I/O pins.

[mongo]

freqmax wrote:
I think a more sustainable model is by delivering a "kit" ie pcb + parts. This should also allow for lower prices, even if Xenepp took a small profit. That will allow people to concentrate on soldering. Some repair shops will do soldering work for pay aswell.

The problem is that the only way it would allow for lower prices is if parts are bought in larger quantities (25+) which would require a fairly large initial cash outlay for the person putting together the kit.

If anyone has an extra few thousand dollars lying around and wants to do so, they could probably make a few bucks profit, but I don't know if it's worth the effort for anyone, especially since I don't know how much demand there would be for a kit. Most people seem to want a pre-assembled one.