The things are simpler than they seem to be

Inside the CPLD there are two independent logic schemes: first controls DRAM (/RAS /CAS, refresh, chip selecting, address multiplexing, etc.), second does autoconfig.
So the amount of memory which physically present is determined by the first part, while the amount found by OS - determined by the second one.
4 and 8Mb differ in first part (for 4Mb, two memory chips are idling all the time) and also by second (4Mb size reported instead of 8Mb).
8Mb non-autoconf in comparison to 8Mb autoconf version, obviously lacks autoconf features =)
New revision will have jumpers to allow you to select 4mb or 8mb, or switch fastmem completely. Also I'm planning trying so-called "slow" memory space (4mb+slow, only slow).
Another improvement is no need to tilt overCPU socket (instead, the board itself is two-level).