The DigROM output is showing that D1 from the DRAMs is not working. Not sure why it's only every second word; as the data bus is 16-bits wide, you'd expect to see two errors in each longword, at D1 and again at D17.
The rev 3 A500 uses 1-bit DRAMs, same as the rev 5 A500 and rev 4 A2000. The DRAM responsible for D1 is U17. I'd start by measuring at U17 pins 2 or 14 (data in and out are connected together) to see if there's any activity present. If not, work backwards to find out where it's broken. If there is data activity at U17, then it's likely defective, so replace U17.
This is either the A500 rev 3 or 5 schematic, the DRAM detail between the two should be much the same. I don't have a better copy unfortunately:
http://amiga.serveftp.net/Schematics/A500_schematics/A500-RAM-ROM-MemExpSlot.jpgAnother way to fault find this is to exchange U17 and U18. If DiagROM shows that the error has moved from D1 to D2, then the original U17 is definitely defective.
