I presume the FPGA used (but not shown in the picture - is it on the other side? Or on another board that connects to the two IDE-like headers? Is there a photo of this other board?) has an on-board DDR3 controller, so it makes sense to use that.
What's the low-end CPLD in the middle of the 68k area for?
I presume the chip on the right is a HDMI driver, displaying a video signal from the lower IDE-like header.
And the Ethernet chip is an SPI/I2S ethernet chip.
Wouldn't it make sense to allow a user to route the HDMI and Ethernet signals to a separate socket they can mount within their case? Or is it oriented so that both are easily accessible?
