Motorola 68060 FPGA replacement module (idea)

[Hattig]

You mean as in ASIC silicon? that would cost at least 40 000 USD, proberbly around 400 000 USD.

The function is not protected as the patents has expired. However perhaps the instruction set opcodes are? but I doubt that to as there exist many other projects in this area without legal problems.

I think he meant having an FPGA on the package. As you say, an ASIC would cost a lot, even if you went for one of the shared-ASIC projects to share the one-off costs with other ASIC designers.

But first, you'd need a design (be it a highly clocked '020 core, or an '060 clone, or the Natami '050/'070 design) that would run acceptably fast on that FPGA, and you'd also need to implement the I/O compatibility with the PGA-206 interface.

[Hattig]

Doing these things, posting about them, and then leaving the work done to die without sharing the VHDL and schematics is very frustrating. They have the right to do it, of course, but it's like being shown a slice of delicious cake and then being told you can't have it.

Edit: Ah, Shadowfire put his work in the EAB file repository.

[Hattig]

The fact that he has got a 68k core running on an FPGA connected into a standard 68k socket and being seen as a standard 68k processor by the system is a great achievement.

As he says, the core can be clocked faster, and it's likely there are a few tweaks to get the per-clock speed up as well. First steps first.

[Hattig]

I noticed his website has been hacked - i hope this doesnt hinder his progress.

http://www.majsta.com/

I just don't understand why someone would do that in this community.

I hope that it was just a random script poking random URLs that found a flaw in the platform he was using for his website.

[Hattig]

Maybe "amiga hardware designs" should be a new subforum of the hardware discussion forum.

[Hattig]

First steps first :-)

First - a 68020 compatible implementation.
Then - a highly clocked 68020 compatible implementation with bigger caches
Thereafter - a higher performance (more instructions per clock) version of the above
Subsequently - an FPU and MMU
Eventually - a pipelined superscalar super-68k FPGA implementation that will fit into an FPGA of a future "Super FPGA Arcade" :-D

I think we're at the second of these currently with Yaqube's work. Each step takes time, especially the third and fifth above - the FPU and MMU might arrive earlier.

[Hattig]

Yes the ALU is a piece you could get from various places ready made. I was pondering the possibility of using the cache management systems out of the OpenSPARC core.

Don't some FPGAs actually include ALUs as hardware on the chip, as they're a common component of the logic that people implement using an FPGA.

However for the non-ALU part, using features from other fast cores makes a lot of sense, e.g., the cache interface and implementation and so on.