Can FPGA 060 run more than 100 Mhz?

[FrenchShark]

Hello,
here are my thoughts about the subject.
First, I think we must have a partially micro-coded CPU instead of a fully hard-wired one.
I have done that with the J68 68000 core and I can achieve a higher clock rate (90 MHz on a Cyclone III, 300 MHz on a Stratix II).
The IPC is quite bad (90 MHz J68 is equivalent to a 30 MHz 68000) but this is mostly due to the instruction decoding not done in parallel and the lack of an address ALU for the EA computation.
Pipelining is good but create a lot of hazards in the pipeline.
Another approach is to create a barrel processor running at 200 MHz with 4 threads.
Then, we need a SMP Exec...
Regards,
Frederic

[FrenchShark]

I've always wondered what a more capable FPGA could do, but the Stratix II is a little too high end for my wallet. Plus its got a lot of capabilities that seem wasted on a 68K emulation project (like the DSPs).
If you REALLY wanted to get extreme, how about Stratix III L?

You can get preatty cheap Stratix I/II NIOS evaluation boards out of ebay.
I have 3 of them : one 1S40, one 2S60ES and one 2S60 ROHS. The last one I got only cost me around 40 bucks (regular price 6 years ago was $1000).
With a friend of mine, we did the cloning of the Atari Jaguar using this board.
Today, the Cyclone V must be as powerful as the Stratis II (ALM architecture with 6-input LUTs).

Price/performance wise, the Lattice ECP3 is not bad either. Plus, it has a DSP block with a dynamic ALU mode that can be very useful in CPU design.

Regards,
Frederic

[FrenchShark]

Compatible with what?
68000, 68020, 68030, 68030+68882, 68040, 68060 or PPC, if you want compatibility with macs they are now using intel processors.
Does faster execution speed break compatibility?

Cache breaks compatibility but if you go with unified cache with snooping, self modifying code is even possible (to a certain extent : you have to take into account the instruction prefetch and the pipeline depth).
If the Amiga chipset is implemented inside the FPGA, you can even snoop DMAs and keep cache coherency over Chip RAM.
Due to the way Exec detects CPU, you can have a core with 68000 exception frame and '020 user instructions (long branches, bitfields, 64-bit MUL/DIV and extra EAs).
Regards,
Frederic

[FrenchShark]

@ Frederic,

I'm having trouble locating Stratix II based developments boards (and most commonly available Cyclone IV boards are crap).
Stratix II and Cyclone III chips are still quite available (at decent prices for the larger chips).
I like the performance benefits of what you have suggested, but it seems like Altera wants to push higher end apps into the Stratix III or higher (and I am not that impressed with the Cyclone V value vs performance ratio).

So, where did you find the dev. boards you have mentioned?

On ebay, you have to check regularly.
Right now there is a Stratix III board for a quite decent price (given the performance of the chip):
http://www.ebay.fr/itm/Altera-Stratix-III-EP3SL150F1152-FPGA-Development-Board-/301153136861?pt=LH_DefaultDomain_0&hash=item461e2030dd.
But keep in mind that you need a full version of Quartus II to run synthesis for this chip.
It looks like you are right about the Cyclone V performance : even with the ALM, it is slower than the III.
This document proves it : http://www.altera.com/literature/ds/ds_nios2_perf.pdf
Regards,
Frederic