Coldfire AGAIN

[FrenchShark]

Hello rkauer,

I wrote a similar emulator (not completely finished) :
Mine is targeted for CF with internal SRAM.
I run the emulation code from it, for two reasons :
- The code is a self-modifying code (I know it is bad but it is so efficient)
- The SRAM is located at address 0xFFFF8000 (the upper 2 GB cannot be used as memory on Amiga) -> the 1024-entry jump table is done with WORDs (move.w xxx,An does a sign extension :-D)

With all these tricks I can achieve an average of 20 instructions per emulated instructions.

Regards,

Frederic

[FrenchShark]

AmigaHeretic wrote:

Sounds very cool.  Are you saying you are emulating all 68k though or you are still just talking about emulating the missing op codes?

I am emulating all 68k opcodes for maximum compatibility.

The core routine is pretty simple :

exec_68k_inst:
  move.w  (A5)+,D6                     ; Read a 68k instruction word
  move.l  D6,D5
  lsr.l   #6,D6                        ; D6 : bits 15-6 (jump table index)
  andi.l  #$3F,D5                      ; D5 : bits 5-0 (effective address)
  movea.w dispatch_tab(PC,D6.l*4),A0   ; A0 : emulation routine address
  movea.w dispatch_tab+2(PC,D6.l*4),A2 ; A2 : effective address table
  move.l  (A2),D0                      ; D0 : offset in the emulation routine
  lea     0(A0,D0.l),A1                ; A1 : patching address
  move.l  4(A2,D5.l*4),(A1)            ; Patch the emulation routine
  jmp     (A0)                         ; Call the emulation routine

Then, the dispatch table:
(first word : routine address, second word : EA table address)

dispatch_tab:
  ;$0000 - $0FFF
  dc.w    inst_ORI_B,ea_ORI_B
  dc.w    inst_ORI_W,ea_ORI_W
  dc.w    inst_ORI_L,ea_ORI_L
  dc.w    inst_illegal,0
  dc.w    inst_BTST_D0,ea_BTST_reg
  dc.w    inst_BCHG_D0,ea_BCHG_reg
  dc.w    inst_BCLR_D0,ea_BCLR_reg
  dc.w    inst_BSET_D0,ea_BSET_reg
  dc.w    inst_ANDI_B,ea_ANDI_B
  dc.w    inst_ANDI_W,ea_ANDI_W
  dc.w    inst_ANDI_L,ea_ANDI_L
  dc.w    inst_illegal,0
  ...

One of the EA table :

;Effective address table for:
; ORI.B  #xx,
; ANDI.B #xx,
; EORI.B #xx,
; ADDI.B #xx,
; SUBI.B #xx,
; CMPI.B #xx,
ea_ORI_B:
ea_ANDI_B:
ea_EORI_B:
ea_ADDI_B:
ea_SUBI_B:
ea_CMPI_B:
  dc.l    2
  lea     reg_D0+3(A6),A0
  lea     reg_D1+3(A6),A0
  lea     reg_D2+3(A6),A0
  lea     reg_D3+3(A6),A0
  lea     reg_D4+3(A6),A0
  lea     reg_D5+3(A6),A0
  lea     reg_D6+3(A6),A0
  lea     reg_D7+3(A6),A0
  dc.w    $4EF8,inst_illegal
  dc.w    $4EF8,inst_illegal
  dc.w    $4EF8,inst_illegal
  dc.w    $4EF8,inst_illegal
  dc.w    $4EF8,inst_illegal
  dc.w    $4EF8,inst_illegal
  dc.w    $4EF8,inst_illegal
  dc.w    $4EF8,inst_illegal
  move.l  reg_A0(A6),A0
  move.l  reg_A1(A6),A0
  move.l  reg_A2(A6),A0
  move.l  reg_A3(A6),A0
  move.l  reg_A4(A6),A0
  move.l  reg_A5(A6),A0
  move.l  reg_A6(A6),A0
  move.l  reg_A7(A6),A0
  dc.w    $4EB8,calc_ea_18_B
  dc.w    $4EB8,calc_ea_19_B
  dc.w    $4EB8,calc_ea_1A_B
  dc.w    $4EB8,calc_ea_1B_B
  dc.w    $4EB8,calc_ea_1C_B
  dc.w    $4EB8,calc_ea_1D_B
  dc.w    $4EB8,calc_ea_1E_B
  dc.w    $4EB8,calc_ea_1F_B
  dc.w    $4EB8,calc_ea_20_B
  dc.w    $4EB8,calc_ea_21_B
  dc.w    $4EB8,calc_ea_22_B
  dc.w    $4EB8,calc_ea_23_B
  dc.w    $4EB8,calc_ea_24_B
  dc.w    $4EB8,calc_ea_25_B
  dc.w    $4EB8,calc_ea_26_B
  dc.w    $4EB8,calc_ea_27_B
  dc.w    $4EB8,calc_ea_28
  dc.w    $4EB8,calc_ea_29
  dc.w    $4EB8,calc_ea_2A
  dc.w    $4EB8,calc_ea_2B
  dc.w    $4EB8,calc_ea_2C
  dc.w    $4EB8,calc_ea_2D
  dc.w    $4EB8,calc_ea_2E
  dc.w    $4EB8,calc_ea_2F
  dc.w    $4EB8,calc_ea_30
  dc.w    $4EB8,calc_ea_31
  dc.w    $4EB8,calc_ea_32
  dc.w    $4EB8,calc_ea_33
  dc.w    $4EB8,calc_ea_34
  dc.w    $4EB8,calc_ea_35
  dc.w    $4EB8,calc_ea_36
  dc.w    $4EB8,calc_ea_37
  movea.w (A5),A0
  addq.l  #2,A5
  movea.l (A5),A0
  addq.l  #4,A5
  dc.w    $4EF8,inst_illegal
  dc.w    $4EF8,inst_illegal
  dc.w    $60F8,$4E71
  dc.w    $4EF8,inst_illegal
  dc.w    $4EF8,inst_illegal
  dc.w    $4EF8,inst_illegal

The emulation routines :

;$0000 - $003F : ORI.B #xx,
inst_ORI_CCR:
  or.l    D1,D7
  rts
inst_ORI_B:
  move.w  (A5)+,D1
  dc.l    0
  move.b  (A0),D2
  or.l    D1,D2
  move    D7,CCR
  move.b  D2,(A0)
  move    CCR,D7
  rts

  ...

Quite straightforward :-D

Regards,

Frederic

[FrenchShark]

@BigGun, AJCopland

Hello,

the software is intended for the 5282 coldfire which has a USP and SSP like the V4 even if it is a V2 core.
The CPU only has 60 MIPS of computing power.

My idea is to emulate all the instructions for maximum compatibility and to rewrite the OS in native ColdFire.
Then, the memory must be divided in two : one part for 68k application (running with the emlator), one part for the CF application. The CF and 68k areas are created by using the special debugging registers, no need for an MMU.
I already rewrote exec.library and partly timer.device in native ColdFire (exec multitasking needs timer to work).
As I said in some previous posts, the biggest issue seems to be the non-atomic access with a CF to IDNestCnt (TDNestCnt is not an issue since it is updated by the taskswitching routine).

I do not want to take any commitment about helping since I do not have a lot of time.

I am also doing some FPGA development, I have a nice idea to make a killing 2D video pipeline with up to 8 independant layers, colorspace conversion, fully configurable DMA scheduler, etc...

Regards,

Frederic