FPGAARCADE minimig compatible board, comments?

[FrenchShark]

Hello MikeJ,

It is funny. I am finishing the same kind of board at work :-).
Even if my board will be used as test equipment for multimedia devices, it is "Minimig capable".
The specifications are slightly different:
- Cyclone EP3C16 QFP-240
- 8 MB of 16-bit ZBT SSRAM
- 30-bit VGA
- Stereo audio output
- 2 joystick ports
- PATA 2"5/3"5
- Configuration done with a DLP2232 board (FTDI chip) or a Propeller add-on board.
For the clock I use a 27 Mhz clock along with a MK2712 chip from IDT that can generate a PAL or NTSC clock.

To minimize the traces lengths between the FPGA and the SSRAM, I put the SSRAM "under" the FPGA with no termination resistor. I already have a similar FPGA-SSRAM design running at 66MHz without any trouble.

Regards,

Frederic

[FrenchShark]

@mikej,

by chance, do you have a 68000 "clone" in VHDL ? (I do not consider TG68 from Tobias as a perfect clone since some 68000 bus signals are missing).
The reason is that on EAB, we were thinking about making an accelerator board for A500/A2000/A600 by using a FPGA.
http://eab.abime.net/showthread.php?t=36596
BTW, I am looking for an A500 to connect to a stratix dev board so I can spy the 68000 bus behaviour with SignalTap II and then replicate it in VHDL (I do not trust 100% Freescale docs :-)).
Any person on this forum can PM me for an offer.
I am in the US, btw.

Regards,

Frederic

[FrenchShark]

Fats wrote:

FrenchShark wrote:
@mikej,

by chance, do you have a 68000 "clone" in VHDL ? (I do not consider TG68 from Tobias as a perfect clone since some 68000 bus signals are missing).
The reason is that on EAB, we were thinking about making an accelerator board for A500/A2000/A600 by using a FPGA.

...

Frederic

I don't think you need to fully implement the 68000 bus signals. If you for example want to make a board for the A1200 you just need to generate the needed signals for the trap door bus. This may save some periphery logic.

greets,
Staf.

Yes, you are right. I checked the A500 schematics and I have seen that at least 7 signals are not used by the A500 hardware :
FC0 - FC2, BG, BR, BGACK and BERR.
Plus, I think, with the FPGA we can get rid of VPA and HALT.

regards,

Frederic