Hello Biggun,
I am also working on a AAA FPGA Amiga but my pace is a lot slower (because of work, family, ...).
Anyway, I thought about the same compatibility issues in my design. Here is what I came up with :
- 16 16-bit channels.
- 2 volume control registers (one for left, one for right).
- Better precision for the period register. I guess your SuperPaula clock will be 28 MHz at least. Even at 28 MHz, you need to have a "fractional" part for the period register so you can generate 32 kHz, 44.1 kHz or 48 kHz sampling rate.
- The 4 standard Paula channels are mapped on channels 10 - 13 (because of the address decoding :-D )
- Have one or two DSPs that can access the chip registers and the chip RAM (or the DMA FIFOs ?) and have their own instruction memory (32KB or 64KB per DSP).
Regards,
Frederic