Floppy emulator

[FrenchShark]

@tnt23

Hello,

I plan to have a full floppy emulation for my stratix II minimig. I want to use the propeller chip from Parallax to do the emulation.

I have some technical questions:
- It looks like every signal has to be open collector with 1K pull-up resistor (because of bus sharing between different drives). Did you do it that way ?
- Paula generates the 500 kbit/s bitrate for the floppy by dividing 3.57 MHz by 7 (511364 bit/s for NTSC and 506699 bit/s for PAL). What frequency do you use for your HW ?
- Did you implement write precompensation ?
- Any support for HD floppy drives planned ?

Regards,

Frederic

[FrenchShark]

tnt23 wrote:
@FrenchShark

- No, I let output signals float. There is a 3-state buffer between my MCU and the bus, and when the emulator is not accessed, it switches its outputs to Z. I simply didn't care much as it worked for Amiga and PC. I guess both have own pull-ups to accomodate any floppy (with or without line termination).
On the Atari ST, however, the emulator failed as there seemed to be no internal pull-ups. I have added a few in a new revision of PCB because of that ST case.

The rule on the computer side is to have a 1K pullup resistor for the inputs. I guess that on the drive side the inputs must have a 4.7K pullup resistor. With your microcontroller, you must drive your signal low or hi-Z, never high. This is for the case you share the bus with another drive.

- My ATmega256 runs at 16MHz. For DD MFM flow, every bit takes 2us, or 32 one-clock 62.5ns instructions. Here is how the output looked in early designs: http://milliways.chance.ru/~tnt23/amiga/mfm.jpg
Now it is much the same, only the "1" are wider.

I have seen that scope trace already. I was surprised by the duty cycle. Was it an issue in your design ?

- I don't do write precomp, mainly for the fact I am not aware of it Can you tell a few words on it?
There is an IDE/Compact flash port in the emulator, which is completely software driven. If I ever manage to use it to attach an external FDD for 'ADF Bakery', I will probably have to deal with write precompensation.

Apparently, write precomp is used for the innermost cyclinders because of the higher bit density. I still need to document myself on the subject. :-P. The best sources seems to be the patents websites and the floppy drive datasheets.

BTW, Amiga Floppy Project (http://www.techtravels.org/amiga/amigablog/) also is based on Parallax chip.

This a SX-48 (a super PIC) not a Propeller.
The Propeller is eight 32-bit RISC CPUs in a chip with 32KB of RAM and 32 I/Os. It is a perfect fit for this kind of application.

Regards,

Frederic

[FrenchShark]

tnt23 wrote:

I will dig the topic. If the precompensation effectively stretches or squeezes timings, it could be handled by just relaxing these when generating/reading bit cell flow.

Yesterday night, I have found more information in the patents : during write, a delay is introduced in the data part of the MFM bit cell. The clock part is not delayed (if you delay both, there is no delay anymore.:lol:). This is done by the floppy drive controller not by the drive itself so, it should not impact your design (maybe some delays would be slightly off during write :-?). Usually, for 2DD floppies, there is no precomp. It is important for 2HD ones.

This a SX-48 (a super PIC) not a Propeller.
The Propeller is eight 32-bit RISC CPUs in a chip with 32KB of RAM and 32 I/Os. It is a perfect fit for this kind of application.

How fast it can be clocked? I was thinking of switching to some low budget ARM chip from Atmel, with at least 50MHz clock rate.

It can run up to 100 MHz. Each instruction takes 4 cycles.
But with 8 cores, you have 200 MIPS of CPU power. You can assign the I/Os to any core. Each core has 2 KB of RAM (512 instructions). There is 32KB of shared RAM to do data exchange between the cores (perfect for buffering a whole track).
You can get the CPU as a DIL40, QFP44 or QFN44. The unitary price is $13.

Regards,

Frederic