FPGA for dummies

[hairy]

It is an emulation in the purest sense of the word because it's not done in silicon but simply by using instructions that are of a lower level than machine language instructions. An FPGA is just a programmable chip just like a CPU, it only serves a different purpose than a CPU.

This is a common misconception due to the fact that you use a "language" to define the circuit. It's really an "hardware description language", not a "programming language".
The program is not executed, it is synthesized. VHDL is inherently parallel (unless you tell it to do otherwise), up to the point you could use most of the chip resources at the same time, in the same clock cycle.
Which is not unusual for massively dataflow designs: consider an array of FIR filters, then you have combinatiorial and sequential logic (and an internal state), but not necessarily a state machine, a sequencer, or a microcode ROM. Hence no CPU.

The short answer was: "what billt said".

[hairy]

"emulation: The low-level simulation of equipment or phenomena by artificial means, such as by software modeling. Note that simulation may also allow an abstract high-level model."
 
"simulation: Simulation is the imitation of some real thing available, state of affairs, or process. The act of simulating something generally entails representing certain key characteristics or behaviours of a selected physical or abstract system."

Applying these rules strictly, a 68000 is just an "emulator" (or "simulator") of the same circuit made with discrete logic, which in turn is a simulation of transistor gates, and so on down to the electron flow level... hmmm yes, this might be true, any Amiga is just "emulating" the original Lorraine boards made out of TTL chips!

FPGA appears to be pretty similar to writing a computer program.

It appears, but it's not. Abstracting the circuit with a program-like listing it's just a convenient human representation.
The only parts of a VHDL (or verilog) design matching your description are testbenches, written in purely behavioural style.
AFAIK it's not possible to produce a working (complex) FPGA design out of purely behavioural description (i.e. like translating a software algorithms and constructs).
Structural VHDL is much more similar to circuit schematic entry and PCB layout, than to a programming language. Despite resembling the latter more.

And you can bake your FPGA to a mass production chip.

Unfortunately it's not that simple. If it was, producing custom ASICs running at 500MHz and more would be one order of magnitude cheaper.

[hairy]

Well, you can do an AND gate using a single relay or two transistors. Using two components made of transistors to make another that can actually be made of fewer transistors seems like imitating the behavior of that made part.

So the ULA chip in Spectrum was "emulating" all other gates different from the basic type available?!? :rolleyes:

[hairy]

Since there were so many members here and elsewhere that were so quick to jump at criticizing A-Eon and Varisys's decision to include the XMOS chip on the Nemo motherboard for the X1000, I thought some of those same people would be able to comment on how they work and what the differences are between them and an FPGA.

Not saying that anyone in this thread was one of those people, but very likely that one or more of those critics is reading this thread.

From what I read at the XMOS site, there chips seem very interesting and the decision to make part of their work Open Source makes it even more interesting.

amigadave,

IMHO the inclusion of the XMOS chip it's not a bad thing per se, what I criticize is:

1) The decision to create an "aura" of magical expectations around its inclusion. It's a poweful chip, but don't expect it to made "the difference" like custom chips did wrt other architectures back in 1985.
2) If you're going to sell the X1000 at *THAT* price, at least be gracious enough to include the top of range XMOS chip available.

As freqmax said, it's probably better to start a new thread because (oh, the shock! the term "emulation" as it was used at the start of the thread (i.e. "algorithmic emulation") it's not only applicable, but better fitting the XMOS chips.

So it could lead to confusion to say that, "yes, it's sort of in between a microcontroller and an FPGA" and on the other hand "one it's emulating, the other is not".

[hairy]

Oh, sorry! I misunderstood.
I thought you intended that when you said "it might be less confusing to not include it in the discussion".

[hairy]

Um, well it depends. If you attached the same DRAM to the FPGA Z80 core, you would get exactly the same behaviour. We could produce a better model of the DRAM by having an access counter per bit, and a pseudo random decay scanner - so yes with enough effort you can do it.
/MikeJ

It might be even simpler, unless aiming for "virtual analog" DRAM modeling

By chance (a bug), I've observed the failed refresh behaviour of a fast page SIMM, and it's amazing how much stuff is still intact after A FULL MINUTE.
So while a small bunch of cells might (or not) fail shortly after the time listed in the datasheet, the number grows much slower than I imagined, no avalanche effect!

All seems to indicate that decay of cells happen with an exponential rate (linked to capacitor discharge curve vs internal noise, I guess).

So probably a couple of LFSRs, a few counters, and some other glue might be sufficient, expecially if the CPU probing for failed refresh is a relatively slow 8-bitter.

[hairy]

You have to look at what the FPGA does here (I didn't ). Is it something that can be ASICed, or is the functionality of the FPGA used in a different way?

Is mostly done in FPGAs because you can update both the CPU firmware and the HW accel functions. Still economically viable considering the cost of midrange and high end routers.
IIRC high end switchrouters (6500 and 12000) also use ASICs.

The functions offloaded to hardware is progressively increasing with the class of the router.
In some midrange models (3600) you can see the effect of FPGA vs CPU processing by using standard vs extended access lists (in reasonably massive amount ).

(recalled from faded memories, please feel free to correct me)