VHDL and Xilinx Software Question.

[RedskullDC]

Hi TrekieJ,

trekiej wrote:
The tutorial in the book show ISE 6.1 software. During Compilation/Synthesis( probably not accurate ) the pins where set by software.
Is it possible to state how I want the pins to connect to my code? During schematic capture it seems to be possible.
...

ISE6.1 is fairly antiquate now.
Suggest you update to the latest WebPack software from Xilinx.com
9.2 is quite stable, 10.1 is getting there...(imho).

Some really handy tools for creating UCF files (where you define pinouts etc.) for a variety of Xilinx based boards can be downloaded from the "PLD Oasis":
http://fafnir.rose-hulman.edu/~doering/PLD_Oasis/software.htm

You basically fill out the spreadsheet, then copy and paste straight to your UCF file.
Saves plenty of time

I've made some versions up for other boards, if the board you have isn't listed there, also added other constraints like drive strength,termination,slew rate.
Here is my Nexys2-1200 version for example:
http://au.geocities.com/redskulldc/UCF_Generator__Nexys2-12.xls


Hope this helps,
Red