On the OP, this sounds like a dumb idea. As said, you're basically doing what Nintendo did with the SA-1 in the SNES game Super Mario RPG: Enhancing one part while leaving the rest untouched.
I really wish Commodore would have diversified the Amiga market. If they made a low cost server with a 68k and OCS combo chip around the time of 1992 then they'd have gotten a toe hold in the low cost server market, especially for people new to server administration. It may have not been super secure, but since Amiga in the 1990s was a poor man's SGI more or less, take a page from their book.
I would like to see the guys at A-EON do a small desktop version of the SGI Onyx2 cube design, and do something like this:
PowerPC or SPARC or MIPS quad core
DDR3 RAM up to 32GB
NUMA bus system
I'm a believer in keeping it simple and staying away from needlessly complex architectures. SPARC, for instance, is RISC, Big Endian and has open designs, plus Fujitsu manufactures tons of them for the server market. SPARC compares favorably to x86_64 if you compare similar die sizes and CPU classes. They're also a parallel orientated design which is where technology is going to move. Moore's law has been hit for clock speeds and the marketing behind that is slowly fading, but we can thank Intel and NetBurst for that, bunch of morons. So parallel, moderately clocked designs will become the norm. Even x86 is now becoming more RISC-like internally, converting the more orthogonal instructions to simpler ones with microcode.
68k was good for the time, where orthogonal instructions were useful, but today all this FPGA design effort is largely fruitless when the fact is the hobby of Amiga computers is going to die out. I like having Nia around, but usefulness is taking priority these days. Orthogonal instructions are largely useless waste of die space when MIPS for instance is simpler by a magnitude and is able to work with the fact that memory access is very fast now and we don't need to have very lengthy instructions fed to the CPU when it is faster now to do short concise instructions. Even Itanium and EDGE emphasize this with instruction parallelism, which while applying CISC concepts to RISC actually compliments the architecture to the point that one engineer I know described it as Super-RISC.