Of course you can do moves to and/or from memory. The 060 has this magical box called "The L1 Cache" which caches all reads and writes for spectacular performance.
Yes, if you only happen to be reading from cache, but once you get a cache miss the whole memorybus stalls for a number of cycles.
If a MIPS-tester can't dual-execute then it isn't testing your CPU. Your 2nd core could be completely broken and you would never know, because that pretend fake MIPS tester wasn't actually testing the 2nd core.
There's not two cores as such, there is the primary and the secondary pipeline. And some of the instructions can only run in the primary pipeline, and even block other instructions from executing in the secondary pipeline.
