You don't create an eval board to debug the chip, you only create one to let others play around with your chip before they use it in your own design, or while awaiting the fabrication of your own design.
Deadlines are made by (project) managers, not by technicians. If I was designing a chip, I would announce it when the developement starts, and write a publication in a newsletter when all major bugs are resolved and i'm fairly sure that i'm able to deliver at this date. You so can count on it that at least the Sa will be available in Q3 2003.
And then it's not hard to modify the Teron PX for the Articia Sa. It's probably done already to test the internal version.
