Hey all,
Would anyone happen to have, or know where I can find some A500 DRAM timing diagrams? I'm interested in all the RAS/CAS/OE/WR stuff associated with the agnus to onboard memory and agnus to trapdoor A501 memory communication.
I looked through the service manuals and hardware reference manual. I've seen diagrams for the 68000 side of Agnus, and some for the other custom chips..... but none that detail the DRAM memory controller.
Any chance that someone here successfully replaced say an A501 DRAM expansion memory with one based on SRAM?
Thanks
No, but would be interested in that myself as I want to create a DRAM tester to test 41256 and 414256 DRAM chip from the A500, A500+, and ST using a PIC chip.
