sorry for wandering off the topic.... (oops)
this got me wondering about what kind of logic would be needed to de-couple the memory bus from the cpu bus, to run the two sync/async to each other a-la 486DX2 - so could have 100Mhz 060, 50Mhz memory.
Then i was thinking of the BPPC. i have a 200Mhz PPC, which is derived from a 3x multiplier of a 66Mhz bus,
but the 040 is a 1/2x (or 060, a 1x) multiplier of a 50Mhz.
does the memory bus switch speeds depending on what CPU is accessing it? or is it locked to either the PPC or 68k bus speed?
Basicly thinking of trying to get round the ram clocking up with the 68k speed, but if this is based off the (i'm guessing here) "double think" Amiga DSP CPU board design, then it is locked to the 68k CPU, so some decoupling logic is still required.
basicly need something like the old overdrive CPU upgrades that allowed a bus multipled CPU (pentium) in a 486 socket, in order to run a 70Mhz+ 060 on a blizzard card...
any other thoughts? or am i talking bull5h1t?... i dunno, i just daydream... :-D
