chip ram was shared between CPU and DMA, so if DMA was active CPU had to wait.
fast ram was in use exclusivelly by CPU, so accessing it didn't requre waiting for DMA.
mysterious slow ram - only CPU was able to generate address for it, so only CPU was able to access it, but the address space from this range was handled by bus for chip ram - so if CPU wanted access from this ram it had to wait for DMA to finish, altough DMA itself was never able to use it.
Good luck
PiR
