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Amiga computer related discussion => Amiga Hardware Issues and discussion => Topic started by: Metalguy66 on January 02, 2015, 03:01:27 AM
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Hi guys. Been a while since I posted on here. I just hacked my CSA Derringer to use a 128meg 72pin SIMM. Thought I'd do a quick write-up for other Derringer owners.
1.)Remove Derringer from the machine.
2.)Remove 68030 from socket (you will be soldering to the back of the 68030 socket pins, so you wouldn't wanna risk heating on the CPU, itself.. Anywayze.. Remove it..
3.)Remove any SIMM that may be in the SIMM socket.
4.)Find U17 on the top side of the board, its located in between the CPU and the SIMM.
5.)Lift pins 12, 13, and 14 of U17 and solder 3 wires, one to each lifted pin. Make these wires about 10-15cm long for now, and carefully run them through the hole (see photo).
(http://www.rasterline.com/images/dmod.jpg)
6.) turn the derringer board upside down and find pin 29 of the SIMM socket.
7.) Get a 27ohm resistor and solder one leg of it to pin 29 of the SIMM socket. Solder the other leg of the resistor to the wire that goes to pin 12 of U17.
8.) Solder the other 2 wires that go to pins 13 and 14 of U17 to pins A4(A28) and B4(A29) of the back of the 68030 socket.
(http://www.rasterline.com/images/dmod2.jpg)
9.) Reinstall the 68030 CPU and SIMM back into the Derringer's sockets.
The SIMM you need is actually 32meg x 32/36 (128megs total).
From the factory, the Derringer can use SIMMs of up to 8meg x 32/36 (32megs total).
Adding the RA11 address line gets us 4x more memory.
I got my 128meg SIMM from Mech of a4000t.com
10.) Install the derringer in the AMIGA.
11.) Boot up the AMIGA. If it doesn't boot, you screwed something up and it isn't my fault.
12.) Get this archive: http://aminet.net/util/boot/addmem301.lha
13.) Uncompress the archive and copy the addmem command to your c: directory on your system boot drive.
14.) Add the following 3 commands to your S:Startup-sequence right after the D3 command. Here's what mine looks like:
c:D3 >NIL: dram drom -mv -ms
c:Addmem >NIL: $18000000 $1A000000 32bit
c:Addmem >NIL: $28000000 $2A000000 32bit
c:Addmem >NIL: $38000000 $3A000000 32bit
c:caches >NIL: +i +d
The D3 command is the normal Derringer command that adds the 32megs, relocates the ROM & vector tables, etc. to 32bit fastram.
The Addmem command here is adding 3 additional 32meg chunks of 32bit ram to the OS's free memory list, at the specified ranges.
The caches command just turns on the 68030 instruction & data caches.
Ok. So that's all there is. It works like a charm for me. If it works for you, great. If not, it ain't my fault.
"You mess with your hardware, you take your chances."
Seeya!
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Are you still living in H-Town? How are you and Fatima doing? Anyway, I have a Fraken500 I need to get to you, to see if we can't clean it up a bit. :)
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Yeah, Martin, I'm still in Houston. PM me.
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Hmm, is that a non sequitur, or an "off thread" post; hard to tell. It can't be a PM without the P part. Could it just be an M?
But the hack sounds great!
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Just so happens I have a spare 128MB SIMM on-hand. I will definitely have to give this a try. Thanks.
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@ Metalguy66 (http://www.amiga.org/forums/member.php?u=5834)
two questions:
1 - "lift pins" does that mean disconnecting them from the board?
2 - Will any 128mb simm work?
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@ Metalguy66 (http://www.amiga.org/forums/member.php?u=5834)
two questions:
1 - "lift pins" does that mean disconnecting them from the board?
Yep. It means CAREFULLY heat pins 12, 13, and 14 of the tiny SMT TSOP package 74F257AD quad 2-1 multiplexer IC at location U17 on the Derringer PCB. As you heat each pin, carefully lift it away from the PCB using a dental pick or similar instrument until it is bent up and no longer contacting the PCB.
2 - Will any 128mb simm work?
As I explained, the Derringer's DRAM circuits are designed to deal with a 72pin SIMM of up to 32megs in size, using an arrangement 8megs x 32 data bits. (or 36 with parity, which it doesn't use). There are 11bits of multiplexed (row/column) address lines going to the SIMM to address 8megs. It then uses the various CAS/RAS signals to determine which of the 4 banks of 8megs on the SIMM it is accessing. What this "hack" does is add an ADDITIONAL address line going to the SIMM for a total of 12.. 12bits of multiplexed addressing gives you 32megs x 32bits. 4 "banks" of 32megs is 128megs. This is the way the SIMMs that the Derringer's DRAM access circuits are designed for happen to work.
Now. To answer your question. Well, there are quite a few weirdo proprietary SIMM standards out there. As far as I know, by the time you get up to 128megs, there is only one JEDEC standard way to do 128megs. That doesn't mean that some manufacturer hasn't built special purpose 128meg SIMMS for some proprietary application that are arranged completely differently. Best I can tell you is that the SIMM you need is:
128megs (32M x 32/36) 72pin SIMM.
If it says that, it should work, but then it must also physically fit. The one I got is a super-thin low profile SIMM. Mine is in an A500, and the whole arrangement has a keyboard laying right on top of it.
Hope this helps.
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Just so happens I have a spare 128MB SIMM on-hand. I will definitely have to give this a try. Thanks.
Yep. The cool thing about this hack is that the 3 pins we are using on U17 are not normally used by the Derringer. So, as long as you follow my instructions and don't accidently mess with anything else, you aren't actually risking anything.
Here's what I mean:
(http://www.rasterline.com/images/derringerdram.jpg)
As you can see, the 4th mux channel in U17 is not even hooked up to anything on a stock Derringer (You DO have to lift the pins in order to perform the hack because the Derringer PCB design has the unused inputs grounded.) So, even after this mod is performed, if you simply re-insert a smaller SIMM (up to 32megs doesn't use the RA11 address line) the thing "electrically" returns to the way it was, for all practical purposes. You don't even have to "undo" the physical mod. It will just be running an "RA11 to nowhere" based on the states of A28 and A29 which won't do a darned thing.
Now, a little about HOW it works. As I mentioned before (and you can hopefully see in the schematic above) we have 11 bits of MUXed DRAM addressing. This means 2 separate strobes of 11bit ROW and COLUMN addresses to each bank of DRAM. These 11 MUXed bits are generated by cpu address bus lines A2 - A23, multiplexed into two sets (ROW & COLUMN) by the 74F257 ICs. So to the AMIGA, we are selecting 8megs by the states of A2 - A23. To get to 32megs, we have some GAL/PAL logic that is controlling when/where the various CAS & RAS strobes are applied and this is based on the state of CPU ADRESS lines A24 and A25 (not shown on schematic because its done inside programmable PAL or GAL logic chips on the Derringer board). This logic also uses CPU address lines A26 and A27 to effectively map the Derringer DRAM to the location $08000000 in the AMIGA's memory address space.
Ok. So what our little hack aims to do is add one more bit of MUXed DRAM addressing and thus go from 32megs to 128megs. This is 2 more bits of CPU addressing. Since I cant change the PAL/GAL logic or what it is doing, A24 - A27 is pretty much off limits. What this hack DOES do is use A28 and A29 which the normal Derringer DRAM access logic doesn't use.
So, what we end up with is 4 sections of RAM, each 32megs in size, but spaced apart in the upper (would be Zorro III) memory space in intervals of 256megs.
So, the first 32meg bank appears at $08000000 to $09FFFFFF (This is where the Derringer's 32bit ram normally appears)
2nd bank appears at $18000000 to $19FFFFFF
3rd bank appears at $28000000 to $29FFFFFF
4th bank appears at $38000000 to $39FFFFFF
This is why we require 3 separate Addmem commands in addition to the normal derringer D3 command, in order to add all the ranges of memory to the system. Amiga OS should absolutely not care that this is the case, and any system legal application should be able to use the ram as contiguous, for all practical purposes.
Whew.. That was a bunch of typing. Hope I didn't make any mistakes or bore you too bad.
Questions? Further Comments? Anyone?
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Mine is in an A500, and the whole arrangement has a keyboard laying right on top of it.
Hope this helps.
Yes, this helps a lot.
My derringer is the 50mhz version. and is sitting in an A500+ :)
I have some problems now with space inside the case. as i have a indivision installed. the two boards collide and argues about some space.
I am looking for ideas to solve the problem. (if anyone got any good ideas I'm listening) And i am on the look for any cpu slot ide controller capable of handling a (or two) CF card(s) for HDDrives.
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Brilliant!
Happy New Year
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Yes, this helps a lot.
My derringer is the 50mhz version. and is sitting in an A500+ :)
I have some problems now with space inside the case. as i have a indivision installed. the two boards collide and argues about some space.
Here is how mine looks
(http://www.rasterline.com/images/dinstall.jpg)
Cant remember what I did to make the indivision ecs fit under it. probably lowered the socket, shortened the standoffs, and relocated any tall components to the other side of the A500+ motherboard.
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I have an Indivision in my A500, along with VXL*30 accelerator. I used a spacer on the CPU socket, it fits fine, also clears the MegaChip I have stuck in the Agnus socket. Case closes fine, although I do have a square of thin foam insulation between the boards and another between the bottom of the keyboard and the top of the accelerator, just in case. VXL looks to be about the same size as the Derringer, although I do wish I had a Derringer instead now that this hack is out! ;)
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I was working on something like this,but not for this card. It was a single sided 128MB or 256MB per simm (custom memory module) but I abandoned it about 4 years ago for speed 28ns.
EDIT: release of 40n EDO memory chips cancelled.
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I will definitely try it. Now i am using 64MB SIMM which D3 detects as 16MB.
The system is stable with it.
Do you think I will get 64MB with this hack?
The SIMM is single sided with 8 chips on it. The chips are MT 4LC16M4H9-5D.
http://pdf1.alldatasheet.net/datasheet-pdf/view/75891/MICRON/MT4LC16M4H9DJ-5.html
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I will definitely try it. Now i am using 64MB SIMM which D3 detects as 16MB.
The system is stable with it.
Do you think I will get 64MB with this hack?
The SIMM is single sided with 8 chips on it. The chips are MT 4LC16M4H9-5D.
http://pdf1.alldatasheet.net/datasheet-pdf/view/75891/MICRON/MT4LC16M4H9DJ-5.html
Well, it depends actually on how it is getting the 16meg. But like I said, there's no reason not to perform the mod. It won't change the way your derringer works with existing SIMMs. All it does is open the possibilities of using SIMMs that have a full 12bits of base addressing.
Now back to the question of the RAM banking. Best case scenario, you could try several ranges and see which one works.
With a single sided SIMM I would *THINK* that its only using 2 RAS signals, but seeing full 11bits of base addressing and so it's getting 2 banks of 8megs. If that is the case, after the hardware mod is done, you should be able to get 2 banks of 32megs each by doing something like:
Addmem $08000000 $0A000000 checkmem 32bit
Addmem $18000000 $1A000000 checkmem 32bit
-or-
Addmem $08000000 $0A000000 checkmem 32bit
Addmem $28000000 $2A000000 checkmem 32bit
If the simm is wired differently, it could work with the following and get 4 sections of 16megs:
Addmem $08000000 $09000000 checkmem 32bit
Addmem $18000000 $19000000 checkmem 32bit
Addmem $28000000 $29000000 checkmem 32bit
Addmem $38000000 $39000000 checkmem 32bit
The datasheet you linked shows that those chips do have the A11 address line, so I would guess one of the first two scenarios to be the case.
When testing, disable D3 in your s:startup-sequence, so that no 32bit fastram is added to the system at bootup. Then, open a shell and try the above Addmem commands with the checkmem option invoked. If any section of ram isn't going to work, it will return an error message within a few seconds. If it doesn't, the system will appear to be locked up while it tests that section of RAM for several minutes, but eventually, it will return you to the AmigaDOS prompt and add the ram to the system (you'll see "other memory" increase at the top of the workbench screen.) After you've done all your testing, reenable D3 in the s:startup-sequence, plus add an Addmem command for each additional ram bank that D3 doesn't find, and this time, no checkmem option. (D3 "finds" the first bank, located at $08000000)
Hope this helps. Good luck![/b]
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I will definitely try it. Now i am using 64MB SIMM which D3 detects as 16MB.
The system is stable with it.
Do you think I will get 64MB with this hack?
The SIMM is single sided with 8 chips on it. The chips are MT 4LC16M4H9-5D.
http://pdf1.alldatasheet.net/datasheet-pdf/view/75891/MICRON/MT4LC16M4H9DJ-5.html
The data sheet you linked shows that the DRAMs on that SIMM have a full 12bits of adressing. So basically, this SIMM is a single sided version of the 128megger. So youve got A2 - A23 (11bits of muxed adressing to the SIMM),A24 uses various CAS signals to determine which 4 of the 8 chips we are talking to for any given 32bit access, but with only single sided, you are missing 2 of the 4 RAS signals, so A25 is nullified. So, yeah, we get to 16meg, but not 32meg. My hack adds A28 and A29 (the 12th bit of muxed adressing to the SIMM)which effectively adds 3 more identicle "banks" using the "upper halves" of all the chips.
Translation: If it's gonna work, here's how it will work:
4 sections of 16 megs each, spread 256megs apart in the adress space.
Addmem $08000000 $09000000 checkmem 32bit
Addmem $18000000 $19000000 checkmem 32bit
Addmem $28000000 $29000000 checkmem 32bit
Addmem $38000000 $39000000 checkmem 32bit
When testing, disable D3 in your s:startup-sequence, so that no 32bit fastram is added to the system at bootup. Then, open a shell and try the above Addmem commands with the checkmem option invoked. If any section of ram isn't going to work, it will return an error message within a few seconds. If it doesn't, the system will appear to be locked up while it tests that section of RAM for several minutes, but eventually, it will return you to the AmigaDOS prompt and add the ram to the system (you'll see "other memory" increase at the top of the workbench screen.) After you've done all your testing, reenable D3 in the s:startup-sequence, plus add an Addmem command for each additional ram bank that D3 doesn't find, and this time, no checkmem option. (D3 "finds" the first bank, located at $08000000)
Hope this helps. Good luck!
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I have desoldered U17. Pin 12 appears to have no trace. Can I cut the traces on pin 13 and 14, so I don't have to lift them? Like on the image that I have attached.
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Very nice mod. Is there any chance to make something like this for other boards like a1200 turbo cards which support only 8megs of ram ?
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JanciB: I have desoldered U17. Pin 12 appears to have no trace. Can I cut the traces on pin 13 and 14, so I don't have to lift them? Like on the image that I have attached.
Yep.
As is customary, 13 and 14 are inputs so they are grounded if unused. 12 is the output so it is just left floating.. But yeah, you can cut the 2 traces to 13 and 14 and then when you replace the IC, you can solder all the pins down rather than lifting 12,13,and 14.
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Very nice mod. Is there any chance to make something like this for other boards like a1200 turbo cards which support only 8megs of ram ?
If you send me an A1200 and said "turbo board" for experimentation purposes, I'll gladly look into it.
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I just finished the mod. It's working!
Added mem with Addmem. Got 64MB with my 64MB simm.
Avail shows largest block 16MB. I think that's normal.
Thanx Metalguy66!
JanciB
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Sweet! Someone should start a Kickstarter to get @Metalguy66 some of those A1200 expansions. We all know the A1200 can address more than 8MB through it's expansion slot, so why the limit on so many of the standard ram/FPU/clock combo cards?
Or is it because of the "EC" nature of the A1200's 68020? I can't recall off-hand, does it only have 24-bit addressing or something?
Now we just need you to make a mod to allow GVP accelerator cards to use anything other than those damned proprietary GVP SIMM's! :hammer:
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Nice work. You wouldn't happen to have similar schematics for the mega midget racer would ya?
Plaz
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@Oldsmobile_Mike,
You ain't whistling in the wind here, My GVP Combo would love more than 16Mb! At least til we get a fast FPGA for the A2000!
Chris
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In response to those asking about the possibility of coming up with an "easy hack" to expand the 32bit fastram on various other accelerators:
It totally depends on the design of the accelerator board in regards to How they are addressing the dram. The CSA Derringer's design just begs to be "expanded". The one extra dram address line that exists on a 72pin SIMM, and that the Derringer's design doesn't employ can be easily generated by simple direct cpu adressing. That isn't always the case, depending on how they are getting the "8 megs" or "16 megs" on some of these expansions. Chip/Bank selection on larger SIMMs depends on the use of multiple CAS and RAS signals (up to 4 of each) which must be generated with specific timing requirements. The Derringer already uses/employs all of these. The addition of these to a design which does not employ them would require additional logic, and almost certainly changes to logic in the existing design. In the case of most accelerators, this means not only adding some ICs to drive the extra signals, but also reprogramming of existing GAL/PAL/CPLD chips to accommodate this.
As far as the Derringer hack goes.. heh. You can thank Steve Kelsey (He also designed the Warp Engine 040). Anyone looking at the Derringer's design would immediately see what I saw. Kind of like a bonus "easter egg" for the future.. In 1991, even a 32meg SIMM was outrageously priced and more ram than most people could find a way to use. But, since 128meggers are available and cheap nowadayze, its nice that the Derringer's design "leaves that door open" for us.
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Since CSA did both the Deringer and M.M.R, I was hoping designs would be similar and most of all you would have docs.
I could add logic if needed, but I'm hoping to cheat by avoiding the reverse engineering steps to save time. :)
Plaz
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Ok, regarding the CSA Mega Midget Racer specifically:
Well, no doubt, if you were to send me the board, I could come up with a scheme to expand it, but theres really no way to do an "easy hack" like the Derringer has. I mean, to add a SIMM to that thing, you are talking 50+ solder points. To "piggyback" or similar, using discrete ramchips would involve even more. Those are most likely 1megx4 ZIPP drams.. So 10bits of address and then some scheme of discrete CAS/RAS signals used to determine which set of 8 chips is being accessed at any given time. You may be able to remobve all the zips and do something similar to what the Amifast ZIPP-SIMM adaptor does. Id have to see the exact access scheme being used in order to say "yes or no" on that. But assuming it is possible, and depending on how much of the 72pin SIMM access standard could be utilized that way, you may then be in a similar situation to the derringer where you could then start making RA10 and RA11 by simply muxing higher CPU address lines and thereby quadrupling total ram with each. This depends on quite a few very big "IFs". In any case, you are talking about a much more involved project than what is required on the Derringer.
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Hi @Metalguy66:
I'm just going to throw this idea out there, hopefully it's not too crazy. ;)
Most A2000-style GVP accelerators can accommodate up to 64MB of ram. At least, their '040 boards. But to do this, you need four of the proprietary 16MB GVP SIMM's. Most people only have the 4MB SIMM's. Your above post gave me this idea: since the accelerator card itself can already support the additional memory, do you think it would be possible to piggyback additional ram chips onto the 4MB modules to "make them into 16MB modules"? Since the actual 16MB modules are rarer than hen's teeth, apparently. ;)
http://amiga.resource.cx/exp/gforce2040
I'd be glad to get a 4MB module to send to you, or send you high res photos of the chips, if you think that would help?
Just want your opinion, since you're the expert on this stuff. Thanks! :D
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1.) I'd need the A2000, the Accelerator, and the RAM.
2.) It would be much more productive to just go ahead and wire in 72pin SIMM sockets. Less connections, less of an unorthodox "ass-rig" and if the dram ever went bad, you'd be able to replace the SIMMs.
3.) You are talking about a VERY involved project. Not something worth writing up for others to easily attempt.
4.) Yes, any machine with at least a 68020 has a 32bit data bus and at least 4 gigs of physical address space. Its just a matter of designing the dram control/address circuits (or modding existing ones) to get the dram on the bus.
5.) I'd be willing to look at anything, and even attempt anything if price is no object, but unless theres already a standard simm socket there, the end result is not gonna be an easily repeatable "hack".
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1.) I'd need the A2000, the Accelerator, and the RAM.
2.) It would be much more productive to just go ahead and wire in 72pin SIMM sockets. Less connections, less of an unorthodox "ass-rig" and if the dram ever went bad, you'd be able to replace the SIMMs.
3.) You are talking about a VERY involved project. Not something worth writing up for others to easily attempt.
4.) Yes, any machine with at least a 68020 has a 32bit data bus and at least 4 gigs of physical address space. Its just a matter of designing the dram control/address circuits (or modding existing ones) to get the dram on the bus.
5.) I'd be willing to look at anything, and even attempt anything if price is no object, but unless theres already a standard simm socket there, the end result is not gonna be an easily repeatable "hack".
Ah, makes sense. I don't know if anyone has ever managed to replace GVP SIMM sockets with standard ones? You've given me something new to look into, thanks! :)
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Avail shows largest block 16MB. I think that's normal.
Sysinfo shows largest block 65MB. I tested it. Created 28MB lha archive in ram:. Without errors. Tested the archive. Without errors. Nice.
J.
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I did some software work for CSA on the MMR. I had a version that supported 2MB of SRAM. I suspect that it was a simple hack like the dram...
512k x8 srams are the same 32-pin dip as the regular 128k x8. should just be a matter of wiring in two extra address lines.
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Ah, makes sense. I don't know if anyone has ever managed to replace GVP SIMM sockets with standard ones? You've given me something new to look into, thanks! :)
they have ;)
http://aminet.net/package/docs/hard/gvpsim64
gvp simms are wired quite different than typical 72 pin simms but its possible to adapt it.
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they have ;)
http://aminet.net/package/docs/hard/gvpsim64
gvp simms are wired quite different than typical 72 pin simms but its possible to adapt it.
I found that this morning, actually. Too bad most of the instructions/pictures are in French. Ah, FML! :laughing:
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I got my 128meg SIMM from Mech of a4000t.com
What is he type of the chips on your 128MB SIMM? Could you make a photo?
Thanx
J.
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This is the 128meg SIMM I use:
http://www.amiga.org/forums/attachment.php?attachmentid=4015&stc=1&d=1424019471
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Hmm, your memory chips are for 3.3V like mine too. Do you think
they can manage 5V too? I did not have problems with mine yet, but there
is duscussion on other forums that 5V can destroy them.
J.
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Yeah, you are right. I never even thought about the possibility of 3.3v SIMMs vs 5v SIMMs.
The GM71V65403CT5 is a 16meg x 4bit dram with 3.3v supply +/- 10% tolerance.
I am measuring 4.5VDC between VCC and VSS pins on the chips, when the SIMM is installed on the Derringer.
That's not good..
If I am unable to find a similar SIMM with 5v rated chips, I may order some small SMT 3.3v regulators and install them inline with the VCC rails on the SIMM, itself.
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4.) Yes, any machine with at least a 68020 has a 32bit data bus and at least 4 gigs of physical address space.
Carefull, it is not "at least 4 gigs", it is a theoretical maximum of 4 gibibytes of physical address space, and in reality less (some address is reserved to chipram for example). Oldsmobile here is very sensitive when it comes to this kind of information.
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Carefull, it is not "at least 4 gigs", it is a theoretical maximum of 4 gibibytes of physical address space, and in reality less (some address is reserved to chipram for example). Oldsmobile here is very sensitive when it comes to this kind of information.
Still trolling? Glad to know I hit a nerve. :roflmao:
FWIW, @Metalguy66 did say "at least a 68020", not the 16-bit data bus / 24-bit address bus 68000, which was the basis for your whole idiotic argument in the first place. :D
Edit: PS - what is a "gibibyte"? :p Also, chip ram reservations are because of the Amiga architecture, not a limitation placed by the processor itself. Man, I can't think of a single accurate statement in your entire post. Bye!