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Amiga computer related discussion => Amiga Hardware Issues and discussion => Topic started by: billt on June 26, 2012, 06:13:48 PM
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Tahoe reminds me (http://www.amiga.org/forums/showpost.php?p=698036&postcount=4) about the Zorro busmaser issue. Is there a list of all cards capable of this busmastering, which could conflict with each other? Is this a Zorro3 issue only, or also Zorro2? (Are there Zorro2 busmaster cards?)
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It's a Buster Zorro3 issue.
I don't have a list, but off the top of my head:
A4091
A4000T SCSI (onboard 4091)
Deneb
Fastlane Z3
DKB 4091
There are Zorro2 busmasters, but I'm not aware of specific problems. I think these just work like normal 68000 busmasters which were pretty well understood.
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Zorro II busmastering is no problem at all, regardless of the number of cards. Fat Buster's design was never really finished.
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There is in other words no fully working Zorro-3 implementation, ever from Commodore?
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There is in other words no fully working Zorro-3 implementation, ever from Commodore?
I ´ve read somewhere that Dave Haynie due to Commodre´s bankrupcy never finished debugging Buster chip adequately. So the best you can get is a Buster revision 11, which still fails under some circumstances.
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The Zorro-3 standard is alright, just not the Buster implementation?
(if so then an FPGA might fix the issue)
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Sadly, yes.
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The Zorro-3 standard is alright, just not the Buster implementation?
(if so then an FPGA might fix the issue)
That's kindof why I asked. :) Expect it to take forever though as time is hard to come by and I have an even more exciting project ongoing.
http://opencores.org/project,zorro_to_wishbone_bridge
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(http://farm6.staticflickr.com/5053/5541783875_6c1b24f572_z.jpg)
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Awesome Zorro bus picture!
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Buster 9 handled multiple bus masters ok if i remember correctly,it had other issues, where as buster 11 had troubles with multiple bus masters.
also the Picasso IV and Zoram belong on the busmaster list i think.
Mech
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also the Picasso IV and Zoram belong on the busmaster list i think.
Don't think they take busmastership though, just Z3 slaves.
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How many gates does the Buster contain approximately?
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How many gates does the Buster contain approximately?
Dave would probably have to try and remember such a thing.
Should fit into an FPGA pretty easily today and have lots of space left over.
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If die size and scale is known. An estimate can be done. It's not just a question of if it can be done. But which FPGA model to choose. Logic capacity, tools, I/O capabiltities and chip package are intertwined.
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Should fit into an FPGA pretty easily today and have lots of space left over.
Sounds like an absolutely heinous task. How do you do a new Buster without breaking a million other things that were designed to work around the original's flaws.
I'm no hardware guru, though. Perhaps someone like Michael Boehmer would be willing to share his insight.
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I'm no hardware guru, though. Perhaps someone like Michael Boehmer would be willing to share his insight.
Yeah he'd be good to ask, also the Elbox guys. Unfortunately none of these people post here really :(
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Sounds like an absolutely heinous task. How do you do a new Buster without breaking a million other things that were designed to work around the original's flaws.
I'm no hardware guru, though. Perhaps someone like Michael Boehmer would be willing to share his insight.
Seen Minimig? Replay? all using various debug tools. Once you got an FPGA wired as Buster you could use it to debug itself and peripherals.
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Seen Minimig? Replay? all using various debug tools. Once you got an FPGA wired as Buster you could use it to debug itself and peripherals.
Indeed. Xilinx has Chipscope. Alteras has SignalTap. Open-Source has Sump, Sigrock, OpenVeriFLA, perhaps others. These go inside your FPGA, and may need some on-board memory to buffer what it measures for later analysis, so you don't need a hugely expensive benchtop logic analyzer tool. If something is off-spec, use one of these things to see what is actually happening, and use your engineering imagination to figure out how to deal with that. Something I really wish I had right now is an FPGA board that plugs into a PCI-Express slot and has another PCI-Express slot on top, acting as a man-in-the-middle spy to capture what goes through it for later analysis. Seems that should not be tremendously expensive, yet quite useful.
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Well shucks I stand corrected, sounds like it's gonna be be a pretty trivial task for one of you guys to knock it out after all. Had no idea it only takes soaring imagination and a debug tool.
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If you make the hardware (or pay for it) I'm convinced others will take care of the (VHDL) coding side of things. The neat aspect of FPGA is that you can make it look for very specific fault conditions, not just a timing diagram or scope picture. But rather if mode X uses byte A4 bit 5 = 1 THEN "****!". And do that really fast which an oscilloscope operator can't cope with.
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Dave would probably have to try and remember such a thing.
Should fit into an FPGA pretty easily today and have lots of space left over.
Dave Haynie has always been quite responsive to stuff like this. Its worth a try to ask him.
Mech