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Amiga computer related discussion => Amiga Hardware Issues and discussion => Topic started by: sim085 on December 12, 2008, 01:27:04 PM
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Hi,
I have some questions regarding accelerator card related to the processors and the memory used on them.
Regarding the processors; where the processors of the accelerator cards all the same. For example the processor 030 on the Derringer and Viper and VXL, GVP530 etc where manufactured by the same manufacturer or they where manufactures by the vendors of these cards?
If they are the same then how come these cards come with different memory configurations; some with 8MB others with 32MB while others with 128MB? Shouldn't all these be able to access the same amount of addresses in memory?
Regards,
Sim085
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although the cpu is the same, each manufacturer made their own "extra chips" on accelerators.
think of it as motherboards with the same cpu but from different manufacturers: others support 8gb ram - others just 4. others have 8 sata ports, others have only 4 and so on... \
it is not the cpu that matters the most, the support it gets is important too.
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So is it possible to upgrade such accelerator cards to support more memory? For example can the M-Tec be upgraded to 32MB of memory? (maybe using the same solution to upgrade the A500+ to 2MB chipram)!
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no. To upgrade the addressable RAM you need to increase the address space of your board. Solder a net which connects the unused address lines on the 68030 to a RAM controller you need to make your own. There's also the issue of drivers for the OS to recognise that RAM. It's not impossible but definitely out of practical possibility. Get a better accelerator.
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(Note that I ask these question to learn the architecture more then because I want to try this out ... I do not have any soldering skills so far).
From my understanding the 030 processor is connected to an (Memory Management Unit) MMU. Now between the processor and MMU there should be all the addresses available to the processor. Therefore the limitation would be between the MMU and the actual Memory chips. Is this right?
Also what do you mean by OS to recognise the RAM? You mean workbench accesses the Memory directly without the use of an MMU?
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The MMU in Amiga systems is rarely used - GigaMem is one that uses it and some remappers, but that's it I think.
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The 68000 cannot connect directly to the RAM. 68000 bus cycles and DRAM bus cycles are not the same.
An interface chip must be used. These were mainly PAL/PLD chips with the logic written by the board vendor.
Most 32-bit 680x0 chips have the full 32-bit address bus which give access to 4Gbytes of address space.
However to save money very few board designs forward all address lines to the RAM sockets.
It's not a matter of passing all address lines to the RAM. The board does some address decoding also.
While a worthy home-brew project I feel that with the lack of documentation you might never be able to work out how the logic on the board works.
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What is confusing me is this; What happened if the processor wanted to store something in an address which was not there? Or this never happened since the processor knew the maximum amount of memory allocated to it?
Also does the operating system talk to these interface chip? or it only talks with the processor? and aren't these interface chips like an MMU?
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the processor doesn't store anything to a location unless it is given to it by the operating system (in this case, exec.device I believe) you need some kind of program which put the extra RAM into available RAM pool. I think all processor boards have a little ROM in them which contains this, ones that do not, (like derringer) you need to run a program at boot to activate the RAM.
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Ok I think I understand (don't do that surprised face please :-)) The operating system would tell the process what instruction to execute and where to store the result and the operating system would know the allowed memory space because of this small program you mentioned. is this right? or I am confusing things?
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yes, you get the picture. there are ways to trap the boot process of an amiga and insert these to the available memory pool. Ralph Babel's Guru Book explains in detail, but it's kind of hard to get a legal copy of that book. But you can find *ahem* other *ahem* versions if you know where to look.
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Thanks, I will try to search for that book.
... just another question about something which has been confusing me a lot ...
In the Amiga Hardware Database there is written that the A500 can only have a maximum of 32MB fast RAM on processor board (i.e. the accelerator card).
http://amiga.resource.cx/mod/a500.html
That said how come the Viper came with 128MB of fast RAM on the processor board? Is the extra RAM for nothing (which I do not think)? and what determines the limit of 32MB mentioned in Amiga Hardware Database?
http://amiga.resource.cx/exp/ematrix530
I think I asked a similar question about chip ram but I am still not sure if I understand this correctly!
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sorry for the long winded rambling reply, but it's friday, and i'm hungover (still), and i'm on a single minded misson to avoid work today.
motorola made the 68020, 68030, 68040, and 68060.
different manufacturers took those chips (GVP, Phase5, SSL, M-Tec etc.) and designed boards, and memory controllers to plug those 680x0 processors into amigas.
and in theory, yes, a full 68030 (and 68020) has access to the full 4GB address range no matter who made the card. however, the memory controller is a different matter.
the GVP A530 for example, memory controller maps its memory to the 8MB zorro2 area in the amiga's address range, and so has a limit at 8MB, as the memory controller cannot address any memory outside of that window.
"back in the day" this wasn't really a problem, as 4MB memory modules cost around £150+. so 8MB of ram was not only a lot, but prohibitivly expensive too. plus it didn't take too much controller logic to map the memory to an area the amiga already had set aside for that kind of thing.
this also has the added advantage that even if you switch off the accelerator, it could act as just a ram card for the 68000 chip as the 8MB is well within its addressable area. however that usually didn't happen, as disabling the accelerator disabled the memory controller it had and there for, the memory as well.
the VXL memory controller can take more than 8MB as it maps outside of the 16MB amiga range, into the 32bit space, but can't understand how to talk to memory modules with higher density cell counts above 32MB, as 64 and 128MB simms were again uncommon, and very expensive, and probably developed later than the card was designed.
The A500 Viper530 also mapped its ram above the standard amiga range in the 32bit area, so was happy to take 128MB on one simm slot as it had plenty of room to map it (i suspect that an additional simm slot would be able to take another 128MB simm quite happily..).
The A1200 blizzardIV/PPC series of accelerators have memory controllers that are again able to map to the entire 32bit range, and, understand double banked simm modules up to 128Mb. and as the A1200 doesn't have to worry about Zorro3 space in the 32Bit address range, so the accelerator has almost the whole 4GB range free to map the memory outside of the standard amiga 16/24bit address space and so can take as much ram as you can throw at it. hence 2x simm slots= 256Mb ram. i'm fairly willing to bet that if you could solder another simm socket or two on there, it would happily use those as well.
The A3/4000 series have a slightly different problem. while they are 32bit, and have the whole 4GB at their disposal, their address range has to take account the zorro3 address space, so they only have 128MB assigned to the CPU slot above the standard memory mapping, then the rest is assigned to Zorro3 address space.
so you can have upto 128Mb on the CPU slot, (a crazy amount when the A3000 was conceived), and up to 512MB addressable per zorro3 slot, with 7 slots with available DMA can take up to 3.5GB of ram. but that all goes through the Zorro3 controller (not as fast as ram directly on the CPU card).
But apparently there is a bug in the exec, and expansion.library that means a machine can't see more than 384MB of ram.
when i say standard amiga memory layout, i mean (as far as i can figure):-
starting from the bottom address
----------------------- start of 16bit area
000000000 - 0001FFFFF .. 2MB chipram
000200000 - 0009FFFFF .. 8MB Zorro2 autoconfig space (16bit/gvp A530 ram goes here)
000A00000 - 000BEFFFF .. Reserved
000BFD000 - 000BFDF00 .. CIA-B even addresses only
000BFE001 - 000BFEF00 .. CIA-A odd addresses only
000C00000 - 000D7FFFF .. 512KB slow ram on A500
000D80000 - 000DBFFFF .. Reserved
000DC0000 - 000DCFFFF .. Realtime Clock
000DD0000 - 000E7FFFF .. Reserved
000E80000 - 000E8FFFF .. autoconfig initialization space
000E90000 - 000EFFFFF .. autoconfig space for I/O boards
000F00000 - 000FBFFFF .. 256KB kick rom (high)
000FC0000 - 000FFFFFF .. 256KB kick rom (low)
----------------------- end of 16bit area
001000000 - FFFFFF000 .. 3.5+GB free for use by 32bit accelerators on non zorro3 machines (VXL etc.)
----------------------- end of 32bit area
otherwise, as a rough guess for A3k/4k machines...
----------------------- end of 16bit area
001000000 - 001FFFFFF .. 16MB mainboard fast ram
002000000 - 009FFFFFF .. 128MB CPU slot area
00A000000 - FFFFFF000 .. zorro3 space from the end of the CPU slot to the top of the 32bit range
----------------------- end of 32bit area
i'm sure someone can correct me on these address ranges where i've gone wrong, but the idea is pretty much there
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I think they only tried to mean that the accelerator with the most RAM on for A500 had 32 mbs. And they didn't think of viper at the time of writing. There is no such limitation for any amiga (maximum ram on accelerator). A4000's have a 128 mb limit, but that is more related to Zorro3 address space, and any amount above 128mb not being able to DMA by zorro boards, AFAIK.
Chip ram is a completely different thing. It is limited by the chipset and it's inability to address above 2mb. To break this barrier you would need to redesign the whole custom chipset.
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From the amiga memory layout there are some things I can understand and some which I cannot (surprise surprise :-))
Always talking from the A500+ perspective (since that is the only machine I have);
'2MB chipram' refers to the 1MB chipram which comes on the motherboard and the 1MB chipram which can be added in the trap door slot.
'8MB Zorro2 autoconfig space' refers to the ram that can be added through for example a side slot expansion such as the GVP A500HD8+ which takes 8MB and the A590 which takes only 2MB if I remember correctly.
'512KB slow ram on A500' I cannot understand ... isnt this the ram that comes on the motherboard and therefore part of the chipram?
'3.5+GB free for use by 32bit accelerators' refers to the memory space that can be on an accelerator card.
Are the above correct; as I said the thing that confused me the most is that 512KB.
The memory table is very helpful to understand the concept. Strange to see that memory wise an A500 can be better equipped (if wanted) then an A4000 :-P
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yes. you got it right. The 512k on the A500 is chip RAM. However, the 512k you put on the trapdoor slot of a regular A500 (not A500+) is slow RAM. There's yet another address space just allocated for A500 trapdoor slot which is 1.8 mb I believe (called ranger memory, or something like that). Normal A500 maps trapdoor memory there. This is neither chip nor fast ram though. It is as slow as chip ram, but not accessible by the chipset, therefore called slow ram.
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sorry, i should have made that bit clearer :-)
the A500+ has one meg on the mainboard, and the 2nd meg in the trapdoor is mapped to the addresses right after it, so you have 2meg continuous chipram, like all machines after it. A600,A1200,A3000,A4000 etc.
The A500 (non plus) only had 512k chip ram on the motherboard, the area where the extra 1.5Mb of the A500plus's ram was mapped as "reserved", and the 0.5MB trapdoor expansion was mapped to the "slow ram" area.
the 3.5GB+ free refers to the available address space that the CPU can get to, _if_ the memory controller can understand that much ram. a-la Viper handing "only" 128MB, but i recon it could do more if it had more simm slots. :-D
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i guess the "ranger memory" is the address space that hasn't been used, but the trouble with this, and "slow" ram, is that it is "fast" ram in that only the CPU can access it, but it is slow in as much as it has to go across the chipram bus to get to it. so ends up having to ask the custom chips for permission to get to this "ranger mem" and hence slower than true fast ram on the side port or accelerator, as that is controlled by the CPU for the CPU.
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Ok thanks a lot to everyone for all the answers. I will need some time to understand all this but things are much more clear now :)
Something else completely different now; What determines the maximum processor that can be used on an Amiga. What I mean is that for the A500 you only find processor up to 040 while for the A4000 you find processor up to 060 (I do not know if more) and even PPC. What determines what type of processor can be used.
Also what is the use to have a processor running at 50Mhz if the socket to which it is connected has only a data transfer of 7.14 MHz (if I understand the specs here correctly: http://amiga.resource.cx/mod/a500.html).
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there are no fixed rules about what kind of processor can be used with an amiga. anything can be used as long as you interact them with proper bus handling. The reason why there are no 060 accelerators for A500 is simply because no one made them, because A500 being the low end of the amiga line, people not being able to afford even and a1200 most probably will never buy a 060 board for a500.
also 68000 bus (A500) and 68020 (a1200) are different in that it is more easy for a1200 to interact with a 68040 bus I belive. But it is possible as there are 68060 boards for A2000, which is a 68000 bus. Theoratically, you can run a PPC accelerator on an A500 with Zorro2 bus expansion, blizzard 2060, PPC developer board.
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@sim085
The operating system would tell the process what instruction to execute and where to store the result and the operating system would know the allowed memory space because of this small program you mentioned. is this right? or I am confusing things?
The memory resources are maintained by the OS (exec.library). At early startup phase the OS pinpoints the amount of chip (at address 0) and ranger memory (at address $c00000). Other memory (accelerators, Z3 etc) is added to the system by AutoConfig(TM) (expansion.library).
When program is loaded, the OS allocates memory from the memory pool for the program sections. The program execution begins at the beginning of the first section.
While running programs can also allocate memory memory dynamically using the exec.library functions. This memory is also obtained from the memory pool. Typically programs also free most of the memory they allocate, returning it to the memory pool.
When the program is finished the control returns to the OS. At this point the OS unloads the program sections, returning th memory occupied by them to the memory pool.
The CPU itself doesn't care what memory it accesses, it accesses exactly what the program tells it to. In case non-existing memory is accessed, several things can occur depending on the CPU and bus type. Older systems (typically 68000 to 68020) have undefined behaviour, the access might go unnoticed, might return random or mirrored content or it might totally screw the system. A3000, A4000, and expanded systems with 68030 to 68060 CPUs typically have more control. With these systems/CPUs accesses to non-existant memory generate an exception which the software can then handle. By default the program just gurus, but in some cases more advances things can be done: For example virtual memory (Gigamem, VMEM) or extra debugging (Enforcer, CyberGuard, muForce).
(This is a slight simplification, but I wanted to keep it understandable. I hope this helps clarify things.)
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Yes but you need the Zorro2 bus expansion because the blizzard 2060 connector is for an A1200 and not for the A500 processor socket right? What I mean is that if (theoretically or fantasy speaking for some) you put an 060 an a board which can connect to the processor socket of an A500 then the processor would still work. or?
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I was talking about something like this (http://amiga-hardware.com/showhardware.cgi?HARDID=1322) which gives an A2000 processor slot (Zorro2 is irrelevant), yes it should work.
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countzero wrote:
I was talking about something like this (http://amiga-hardware.com/showhardware.cgi?HARDID=1322) which gives an A2000 processor slot (Zorro2 is irrelevant),
Yes I understood that; what I meant is that you need one of those to connect a blizard 2060 because the connector is different then the connector of an accelerator card for the A500.
countzero wrote:
yes it should work.
I do not want to push it but does this also apply for a PPC? I know you already said it should work in your previous post. However I was thinking that a PPC recieves instructions in a different way then an 680X0 processor. If so then only an OS which can send such instructions can work (example OS4.0) and I do not know how much you could fit that on an A500 with a PPC.
Again I must repeat that this is just hypothetical speaking. I am just trying to understand the concepts behind accelerator cards not actually thinking to build one since I have no electronics experience ... sorry for any one who was hopping for that ... maybe one day in the future ;-)
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well maybe you should see for yourself ?
Amiga 2000 with PPC (http://uk.youtube.com/watch?v=foWfXhmi1wY)
An amiga 2000 is basicly an A500 with Zorro2 slots and buster. They have the same 68000 based bus. If it works on an A2000, it should work on an A500.
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but how is it possible ... how can the same instructions used for the 680x0 processor also work on a PPC processor? I can understand between different 680x0 processors but not between completely different processors!
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you misunderstand. The 68k code does not run on PPC. Only specifically compiled PPC code runs on PPC. The main OS runs on 68k. But some parts (computation heavy stuff like jpeg, mp3 decoding, etc) have special libraries which run on the PPC cpu. This is the case for OS 3.9 (an 68k OS)
OS 4.0 for classics is different though. It runs totally on PPC cpu. 68k programs also run on an 68k emulator on PPC CPU.
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aaaa ... i checked the video again and he puts the 68060 processor back on the PowerUp Dev board...
This is such an interesting subject and I personally could keep asking one question after the other :-)
Thanks for all the answers ... there is much to think about after this thread :-)
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@sim085
Yes but you need the Zorro2 bus expansion because the blizzard 2060 connector is for an A1200 and not for the A500 processor socket right?
Blizzard 20x0 connects to the A2000 CPU socket (CPU Fast Slot). A500 doesn't have it, although some rare expansion units give it.
http://www.amiga-hardware.com/showhardware.cgi?HARDID=174
But seriously: While A500 with PPC is in theory possible it really isn't worth the trouble. :-)
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Piru wrote:
But seriously: While A500 with PPC is in theory possible it really isn't worth the trouble. :-)
I understand that and I do not have plans to put a PPC into my A500+ :-) I am just trying to figure out what the limitations are.
However one can imagine (or a better word is 'fantasies') an accelerator card which can emulate different processors ...
You can have a board with any type of processor on top of it and some extra ram as well. the processor would actually run only a single program which would be an emulator. The instructions received from the Operating System would be translated and then executed. Like this you can have a single board which can be configured as a Viper, Derringer, Blizzard, etc ...
I know some will say why not use WinUAE and get it done with, but would something like the above be possible?
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Blizzard 20x0 connects to the A2000 CPU socket (CPU Fast Slot). A500 doesn't have it, although some rare expansion units give it.
The A2000's CPU slot and the A500's expansion port are actually very much alike - something like a simplified Zorro II slot w/o AutoConfig.
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@sim085
I know some will say why not use WinUAE and get it done with, but would something like the above be possible?
Sure it would, but the price would be so hideous you could get a couple of recent AMD or intel setups for the price.
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Piru wrote:
Sure it would, but the price would be so hideous you could get a couple of recent AMD or intel setups for the price.
Yes I know what you mean ... and as I already said I do not have the knowledge nor the time to do something like that ... it was just a (quick) thought after all the posts :-)
However it was nice to learn so many things on accelerator cards and more importantly on how memory was managed in the Amiga.
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Let me explain the problem on the real side of life: I'm developing an A600 020 accelerator.
A major PITA, if you ask me. The RAM controller is small and fits on a little portion of a (nowadays small) PLD.
The other parts of it are implement/interface signal buses not present on the 68000 side and required for the 68020 to work. And the leftover is dedicated to new IDE controller (for A500/2000 in a future version).
Guess what? I had to stop development for lack of... funds! No, I am not asking for nobody's money. I will not accept pre-orders nor any other type of "donations".
Prototyping a board is time-consuming and expensive. Just for your information, a single small prototype board will cost around 500 USD, without any component placed on it.
Now imagine a powerful 060 or even modern CPU: the prototype board will cost securely more than 1000 USD for a single board.
Get the picture? :horse:
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@rkauer
So an empty PCB costs that much!!? How does it work? you send the PCB design to a company and they send you the empty PCB board? or?
I do get your point however. I started this thread just to get a better understanding about Accelerator Cards. I do fantasies some times of building one myself when I will have the time to learn how to do so; however such a time is very far away at the moment ... if it will ever come close I do not know!
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I wonder who has the rights to the previously sold cards as I think some of the companies are out of business.
If the patent and copyright was assigned to a company ,and said company is not acquired by another does the patent pass into public domain ?
If someone produced clones of a product from a defunct company what would happen ?
On the technical side I've not worked with SMD ,the old discrete and 0.1" pin spacing of DIP were challenging enough for my eyes!
Note: I am not a lawyer nor do I play one on TV.
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@recidivist
Even if you somehow would avoid the legal problems, you'd still be unable to produce the clones: The components are no longer available.
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Piru wrote:
@recidivist
Even if you somehow would avoid the legal problems, you'd still be unable to produce the clones: The components are no longer available.
@Piru: a lot of ancients components are available at small quantities on those Ebay companies and on-line stores.
But even if someone collect enough "material" to copy a card, where someone grab the code of PAL/GAL/PIC used at that time? Those chips have read-protection, so you can write to it, but not read the contents.
And another not-so-minor problem: ROHS! This acronym means no new electronic product sold on Europe can have lead (solder and chips). So goodbye for the old chips, anyway... :headwall:
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@rkauer
I am afraid this thread (like many others) will turn into a 'why not build a new accelerator card' type of thread.
However I cannot stop myself from asking this; Are you keeping some sort of diary on your progress? Do not get me wrong, I am not asking this to see when the card you are creating gets ready (I have an A500+ so it would not even be compatible I guess) but rather to know what needs to be done to actually go through a project like this one; what are the difficulties, how to solve them, the various tasks and so on. I think that would be an interesting read :-)
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Read protection on the chips ? I had thought only legal and parts issues prevented cloning and reading chips no different than reading out ROM. :-?
Lack of the glue code is a showstopper.
It is a shame abandoned IP doesn't automatically become public domain.
The copyright and patent laws of the U.U. of A. were originally much more limited in time and that was for an era commerce moved much slower!
Use it or lose it!
Everything is so complicated these days,especially by enviromental and safety rules that attempt to remove all possible risks.We? now worry about substanc in parts per trillion as a hazard yet just a century ago were commonplace with little noticeable effects.Just look at the lead paint,DON'T eat it,and I bet you'll be fine!
Anyway,modern multilayer pc boards are hardly a home project and setup costs are a huge factor in small production.
Now here's a project to contemplate: an adapter or inbetween card that plugs into the cpu slot of classic Amigas and then has the slotfor an Apple Mac cpu or upgrade cpu .
:-o
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rkauer wrote:
Prototyping a board is time-consuming and expensive. Just for your information, a single small prototype board will cost around 500 USD, without any component placed on it.
A single small prototype board will cost you nowhere near that.
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I've found a Chinese supplier for the board: 100x100mm, 4 layers, ROHS-compliant, less than 400 holes, SMD solder on both sides, silver plated (ROHS demmand), 0.1mm spacement high-density traces. ~280 USD, without shipping and custom fees!
Brazilian industries take advantage of the custom fees (~107% !!!) to sell prototype boards for the price they want (a bit less than imported ones).
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For people whiling to learn about how to make your own accelerator, and starting with a good electronics acknowledge, read:
Lucas/Francis project;
then Freescale's 68000, 68881/2, 680EC020, 68020 and 030 datasheets. Also DRAM memory principles and controllers, CPLD, GAL/PAL & PIC datasheets and programs. That's for start...
Oh, and also you need to learn a PLD language, like verilog.