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Amiga computer related discussion => Amiga Hardware Issues and discussion => Topic started by: A6000 on November 23, 2007, 02:28:51 PM
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I would like to see some of the talented designers on this forum design a replacement motherboard for the amiga 4000D.
Many systems are being eaten by battery and capacitor ooze, and will not last another 15 years.
The board should have a minimig FPGA to replace the AGA chipset, it would start with ECS but later could be reprogrammed for AGA, AAA or HDTV feature set, with akiko chunky to planar conversion.
There would be a socket to take either an 040 or 060 with a jumper to select 3.3v or 5v cpu voltage.The clock speed could start at 25mhz and be raised through the bios, there could be sixteen speeds ranging from 25 to 120mhz for easy overclocking.
The board could use DDR2 ram - 2GB - all chip ram.
And I suppose we might as well put a cheap PPC on it.
The Walker used a Multi I/O chip which could simplify the circuit, but the unreliable CIA's have been incorporated in all amigas since the A1000 are they indispensible because of code in Kickstart?
The hard drive interface should be either ultra ATA/133 or SATA 2/300 either would be faster than the old scsi drives we may be using now, and an SCSI controller could be plugged into the zorro bus if necessary.
Eventually there could be replacement mainboards for all big box amigas. If we were to produce an ATX board our systems would look the same as any "dead common" pc, and I don't think any of us wants that! :-)
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Will you be financing this ambitious creation?
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This would be a volountary project, a "hobby" if you like.
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I am sure that anyone who thinks they can make a profit supplying bare or ready bult boards will put in whatever money is needed.
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Sounds nice! But I'm afraid that it's a bit unrealistic. Let's just start with AGA and a faster processor?
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I don't necessariyl disagree with your ambition but I think that you're going to need to put some effort in yourself if you want to get this started.
Firstly however a couple of things. SDRAM PC100 or PC133 is seemingly much easier to implement and is on my own list of things todo right after "build my first MiniMig v1.1". DDR and DDR2 has been mooted as difficult for hobbyists due to timing constraints. So for now I'd stick with SDRAM, its cheap and plenty fast enough for MiniMig.
Forget sockets and just go straight for an '060 if you're wanting to upgrade the CPU. It makes the design easier as its running at the same 3.3v as the FPGA so theres no level shifting.
CIA's are, as far as I know, replicated within the FPGA using Verilog. No need for anything external.
To support AGA and '060 you're gonna need a 32bit data bus, might as well support a 32bit address bus at the same time. That means quite a few more pins available on the FGPA so you'll be going to BGA based FPGA.
ATA/100/133 IDE is nothing I've heard talked about so I don't know how much harder it'd be than any other IDE mode.
Zorro support. I have not a clue :-D
Basically I think that if you want to see this become a reality then you should break it down into the tasks required for each stage. Once you've done that pick the first one that you feel is crucial and look into the parts and things that you'd need to change to make it happen! You don't need any experience to that bit but it'll mean that when you come back and need experienced help you've done most of the legwork!
Good luck.
Andy
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AJCopland wrote:
Firstly however a couple of things. SDRAM PC100 or PC133 is seemingly much easier to implement and is on my own list of things todo right after "build my first MiniMig v1.1". DDR and DDR2 has been mooted as difficult for hobbyists due to timing constraints. So for now I'd stick with SDRAM, its cheap and plenty fast enough for MiniMig.
Forget sockets and just go straight for an '060 if you're wanting to upgrade the CPU. It makes the design easier as its running at the same 3.3v as the FPGA so theres no level shifting.
CIA's are, as far as I know, replicated within the FPGA using Verilog. No need for anything external.
To support AGA and '060 you're gonna need a 32bit data bus, might as well support a 32bit address bus at the same time. That means quite a few more pins available on the FGPA so you'll be going to BGA based FPGA.
ATA/100/133 IDE is nothing I've heard talked about so I don't know how much harder it'd be than any other IDE mode.
Zorro support. I have not a clue :-D
Basically I think that if you want to see this become a reality then you should break it down into the tasks required for each stage. Once you've done that pick the first one that you feel is crucial and look into the parts and things that you'd need to change to make it happen! You don't need any experience to that bit but it'll mean that when you come back and need experienced help you've done most of the legwork!
Good luck.
Andy
Well I will admit that this task is beyond me, but well within the capabilities of others on this forum. but I would start with the circuit and pcb design of the 4000D and:-
1. replace fast slot with cpu socket, this can accept 040 or 060 since there will be more 040's available than 060's. the programmable clock speed allows any speed version to be used.
2. replace AGA chipset with minimig FPGA.
3. implement memory, SDR is old and expensive, DDR2 may be more economical.
4. implement hard drive interface.
Job done?
P.S The PPC can go on a board plugged into the cpu socket.
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I am sure that anyone who thinks they can make a profit supplying bare or ready bult boards will put in whatever money is needed.
There is no large scale profit, which is why no-one is mass producing MiniMigs.
I'll do it for £15k upfront, which will be paid back on first sign of a profit.
They still make both 040 and 060. I've bought E41J 060's before at €75 each. No-one will care about 040.
I know the 060 is 3.3v core voltage but I think it still has 5v I/O
Freescale Data (http://www.freescale.com/webapp/search.partparamdetail.framework?PART_NUMBER=MC68060RC50&buyNow=true)
SDR is still cheap and sold in very high quantities as it's in everything from DVD players to washing machines.
Personally I would prefer MegaMig. A MiniMig form factor with an 060.
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Akiko wrote:
Will you be financing this ambitious creation?
This project isn't ambitious enough for the amount of work necessary. I do agree that if A6000 wants to get this started he should put up some of the funds though.
A6000, the project you want isn't best served with a Minimig-based solution, you'd be much better off with Clone-A.
http://www.amigahistory.co.uk/clone-a.html
Only mentions OCS in that link, but AFAIK work on AGA is well under way.
Way I see it is Clone-A and Minimig complement each other. Clone-A is about perfect reproduction of the past, whilst Minimig (+AROS) gives an opportunity to take complete control of the future.
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Let's call it Maximig :-)
Seriously, my remarks:
- 2GB of Chip RAM will break compatibility, the Amiga architecture is limited to 8 MB of Chip RAM due to the memory map.
- To limit the the number of I/Os on the FPGA you can use the 040/060 in multiplexed bus mode (32 wires for address and data instead of 64).
- A coldifre is less expensive than a 040/060 and you can achieve a 100% accurate emulation (not the illegal instruction hack) with an average of 20 CPU cycles per instructions.
- A drop-in replacement of an A4000 board will be very expensive because of the board size, most of the PCB will be empty since the FPGA can integrate most of the A4000 components.
- Using a off-the-shelf evaluation board is less expensive: Altera is selling its NiosII evaluation kit WITHOUT the software for $395. The Altera FAE told me that the new Cyclone III NiosII evaluation kit should be available for December. It should integrate a VGA output. The price is still $395.
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Ok, fine, my 2 bits:
You must crawl before you can walk. I am working on an A500-like expantion bus for my MiniMig, you'll need that before even trying Zorro III. You'll need ECS before you get AGA, so someone needs to make ECS. Come on guy, be realistic. You have to take these steps first.
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downix wrote:
Ok, fine, my 2 bits:
You must crawl before you can walk. I am working on an A500-like expantion bus for my MiniMig, you'll need that before even trying Zorro III. You'll need ECS before you get AGA, so someone needs to make ECS. Come on guy, be realistic. You have to take these steps first.
ECS is in the minimig FPGA which is used in place of the AGA chipset, it may be possible to reprogram this later to be AGA as I said in my earlier posts.
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A6000 wrote:
downix wrote:
Ok, fine, my 2 bits:
You must crawl before you can walk. I am working on an A500-like expantion bus for my MiniMig, you'll need that before even trying Zorro III. You'll need ECS before you get AGA, so someone needs to make ECS. Come on guy, be realistic. You have to take these steps first.
ECS is in the minimig FPGA which is used in place of the AGA chipset, it may be possible to reprogram this later to be AGA as I said in my earlier posts.
Only if you supply an FPGA large enough. The current FPGA is not. How about we get an A2000 replacement going first, then let's work on the next step?
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FrenchShark wrote:
- A coldifre is less expensive than a 040/060 and you can achieve a 100% accurate emulation (not the illegal instruction hack) with an average of 20 CPU cycles per instructions.
Yeah right... NOT!
Emulation is good in a closed environment, as soon as you introduce external inputs, interrupts, exceptions etc. the house of cards comes tumbling down.
If it was possible and the speed was anywhere near a 50MHz 060 we'd have Dragon(?) boards by now.
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A6000 wrote:
ECS is in the minimig FPGA which is used in place of the AGA chipset, it may be possible to reprogram this later to be AGA as I said in my earlier posts.
MiniMig is not ECS, it is currently a slightly buggy OCS. (Still great work though, a major achievement!)
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FrenchShark wrote:
- 2GB of Chip RAM will break compatibility, the Amiga architecture is limited to 8 MB of Chip RAM due to the memory map.
It should not break compatibility, the zorro III bus can have 1.75GB of fast ram, the 2GB ram would be used as fast ram with DMA and a smaller block of this ram is used for graphics and sound, whether that is limited to 2MB, 8MB, or more remains to be seen.
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downix wrote:
How about we get an A2000 replacement going first, then let's work on the next step?
The responses to this thread have been so negative that nothing will be done.
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A6000 wrote:
downix wrote:
How about we get an A2000 replacement going first, then let's work on the next step?
The responses to this thread have been so negative that nothing will be done.
Oh, that's a great, positive attitude!
Look at other threads, work is being done by more than one member and the MiniMig is going to lead to several different, enhanced projects.
It will take some time, but look at what has already been done, alone by Dennis in just one year, where no company, or group of developers has been before. It has inspired others to take action and build on top of what Dennis has started.
Even Dennis is adding to what he completed by working on multiple adf support.
The future of Amiga development has never looked so good!
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A6000 wrote:
FrenchShark wrote:
- 2GB of Chip RAM will break compatibility, the Amiga architecture is limited to 8 MB of Chip RAM due to the memory map.
It should not break compatibility, the zorro III bus can have 1.75GB of fast ram, the 2GB ram would be used as fast ram with DMA and a smaller block of this ram is used for graphics and sound, whether that is limited to 2MB, 8MB, or more remains to be seen.
Most of the games expect the Chip RAM to be located at 0x00000000. According to the memory map 10MB are available from 0x00000000 to 0x009FFFFF. So a max of 8MB of Chip RAM can be used (managing the remaining 2MB with the chipset will be a pain).
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alexh wrote:
Yeah right... NOT!
Emulation is good in a closed environment, as soon as you introduce external inputs, interrupts, exceptions etc. the house of cards comes tumbling down.
If it was possible and the speed was anywhere near a 50MHz 060 we'd have Dragon(?) boards by now.
According to my tests, the speed is near a 25MHz 040.
Maybe Elbox dropped the project or they are busy re-writing the KickStart with coldfire code.
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A6000 wrote:
downix wrote:
How about we get an A2000 replacement going first, then let's work on the next step?
The responses to this thread have been so negative that nothing will be done.
Actually you're replying to Downix who has started to do something. He's right though that you've got to do these things in little steps because that's how you make sure that they actually get done!
Andy
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A6000 wrote:
Well I will admit that this task is beyond me, but well within the capabilities of others on this forum. but I would start with the circuit and pcb design of the 4000D and:-
1. replace fast slot with cpu socket, this can accept 040 or 060 since there will be more 040's available than 060's. the programmable clock speed allows any speed version to be used.
2. replace AGA chipset with minimig FPGA.
3. implement memory, SDR is old and expensive, DDR2 may be more economical.
4. implement hard drive interface.
Job done?
P.S The PPC can go on a board plugged into the cpu socket.
Someone else has already stated it but you're talking about something like the Clone-A. Where you start by replacing each of the chips in an A4000D motherboard with fpgas and "just" duplicate the motherboard design.
That won't really work for several reasons. The main one being duplicating the motherboard design as it isn't really easy or possible for hobbyists and it's not economical for a professional company.
Don't let that be the end of the idea though.
What I meant in my reply was to start from the MiniMig v1.1 as your base. Decide what you want and then figure out what you'd need to do to change the v1.1 into the thing which supported that idea. Then you move onto the next part of it and do the same. Repeat until you've got all of your features and voila! You'll have got a MiniMig4000.
Also as someone already said, SD-RAM is still cheap and plentiful due to its use in just about everything from washing machines to set-top-boxes. Also for the speed of the 060 and PPC chips its plenty fast enough. DDR can come later but start off easy!
For the A4000D you'd want what? an '060? Ok figure out how to add that, just with pen and paper compare what the MiniMig has now and what you want it to have. Go and lookup the datasheet on the Freescale website and see if as alexh says it uses 3.3v or 5v for it's IO lines. If it does use 5v then you know that you'll need voltage shifting hardware.
Make all of the things that you discover into a list of things that you _reasonably_ think you'd need to do, but don't know how, to put a 68060 processor onto a MiniMig v1.1 physically. Don't even worry about the code used in the FPGA for now just think about that one small area.
Once you done that, come back and ask again about how to actually do those things or see if someone would be willing to design them for you. Basically get someone to sanity check them.
Andy
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downix wrote:
How about we get an A2000 replacement going first, then let's work on the next step?
An A2000 clone Minimig (with the expansion options) is what I see as the next major step forward for the Minimig. I'm working on something now that needs A2000 compatibility, so of course I'd say that!
A6000, the negativity is arising because you need to think practically about this project idea. I appreciate you've said that you're not able to help with the technical aspects of implementing your design, so why not do something about that? I've started to learn Verilog so I can help, using this tutorial, I recommend you do the same:
http://www.asic-world.com/verilog/veritut.html
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@HenryCase,
Well said!
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It seems like we've had this same discussion dozens of times already. There are several threads just like it on A.org. Basically, someone says the minimig is underpowered/crap/great-but-could-be-better and then suggests some super fantastic minimig be developed straight away.
The responses from those who actually *work* in electronics/computing hardware development are always the same: development takes time, in small, realistic steps.
I totally agree. Zorro (or other expansion bus) first, then AGA, then a faster processor and onward. Make sure each development works, then move onto the next step. MiniMig A2000, MiniMig A1200, etc. etc. It takes little steps.
Even the Great Pyramid at Giza was built one brick at a time.
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Work on Clone-A is still ongoing and progressing - but this project will hopefully make commercial Amiga hardware more viable.
Clone-A is intended to be a cycle exact representation of the Amiga hardware.
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HenryCase wrote:
downix wrote:
How about we get an A2000 replacement going first, then let's work on the next step?
An A2000 clone Minimig (with the expansion options) is what I see as the next major step forward for the Minimig. I'm working on something now that needs A2000 compatibility, so of course I'd say that!
A6000, the negativity is arising because you need to think practically about this project idea. I appreciate you've said that you're not able to help with the technical aspects of implementing your design, so why not do something about that? I've started to learn Verilog so I can help, using this tutorial, I recommend you do the same:
http://www.asic-world.com/verilog/veritut.html
If you want the CPU fast-slot I have the design 90% done with my neo-A500 sidecar slot design.
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amigakit said:
Work on Clone-A is still ongoing and progressing - but this project will hopefully make commercial Amiga hardware more viable.
Amigakit, I'm glad to hear progress is still being made on the Clone-A, haven't had much news around for a few months, have you heard anything from Jens or Oliver recently?
amigadave said:
Well said!
Thanks amigadave! :-D
downix said:
If you want the CPU fast-slot I have the design 90% done with my neo-A500 sidecar slot design.
Thanks downix. As it happens it is the A2000 CPU slot that I need for my project. Is this really very similar to the A500 sidecar slot?
I don't want to say too much about my project at the moment, because it might not come to anything, still very early days. When I've got some concrete signs of progress I'll be posting on a.org for assistance.
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HenryCase wrote:
downix said:
If you want the CPU fast-slot I have the design 90% done with my neo-A500 sidecar slot design.
Thanks downix. As it happens it is the A2000 CPU slot that I need for my project. Is this really very similar to the A500 sidecar slot?
I don't want to say too much about my project at the moment, because it might not come to anything, still very early days. When I've got some concrete signs of progress I'll be posting on a.org for assistance.
yes, only 2 pins different. So, close enough that it can easily be adapted.
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According to my tests, the speed is near a 25MHz 040.
Out of interest, which Coldfire and 68k emulator do you use? And what code did you use for testing?
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All 68040 I a have seen are 5V and are hardobtainium. And when a 3.3V (=less pcb, less cost) 75 EUR, 68060 is available. It doesn't make sense to wad into the 5V swamp.
SDRAM is reasonable effort, but DDR2 is a pain to get working due impedance match, risetime considerations etc.. So rather more sdram chips than ddr modules that will proberbly be more unreliable for electronics hoppyists.
If using PPC is a design decision, Xilinx Virtex is proberbly the most optimal solution (fgpa + cpu in one chop
package)
To get SATA, I have not found any SATA PHY (physcial interface for fpga. So PCI interface seems the most sensible. Possible with a PCI<->Amiga hw translator.
ATX size doesn't imply uggly design per se. You can fit a small board within a larger A4000 case.
Sockets might work on <10MHz Minimig v1.1, but on a >25 MHz A4000 it's deep water. It will distort the signals and hinder any serious performance. SMD soldering is just a fact of life in modern highspeed electronics.
The Coldfire CPU is incompatible in a way that makes it messy to use, Better spend that energy on a m68k verilog/vhdl clone. Which will free a chip and associated support circuitry.
We'r not trying to say it's impossible Just that some issues will have to be resolved before it can continue. And that some choices are more realistic than others.
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Donar wrote:
According to my tests, the speed is near a 25MHz 040.
Out of interest, which Coldfire and 68k emulator do you use? And what code did you use for testing?
You could make it near native with a hardware translator.
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Donar wrote:
According to my tests, the speed is near a 25MHz 040.
Out of interest, which Coldfire and 68k emulator do you use? And what code did you use for testing?
The coldfire : the fastest (MCF548x) : 400 MIPS.
The emulator : my own emulator, it has to run from the internal SRAM of the coldfire. It uses self-modifying code.
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downix wrote:
HenryCase wrote:
downix said:
If you want the CPU fast-slot I have the design 90% done with my neo-A500 sidecar slot design.
Thanks downix. As it happens it is the A2000 CPU slot that I need for my project. Is this really very similar to the A500 sidecar slot?
I don't want to say too much about my project at the moment, because it might not come to anything, still very early days. When I've got some concrete signs of progress I'll be posting on a.org for assistance.
yes, only 2 pins different. So, close enough that it can easily be adapted.
That's great news downix. Fingers crossed your Minimig improvement project goes smoothly.
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Thank you freqmax for your informative post.
Some considerations that shaped my original post were:-
1. new 060's are expensive if you accept the prices given on freescale's website, so people may want to obtain "pre-owned" 040's or 060's.
2. users may want to walk into their local pc supplier and buy a replacement memory module that will work in the new board, in this respect, SDR modules are in decline, however, the concensus appears to be that SDR chips are the way to go, and I won't argue with that.
3. An open source community project is more likely to produce something that the community wants, rather than what is most profitable but not quite what the users wanted.
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You could make it near native with a hardware translator.
You mean a device that translates 68k instructions to the appropriate Coldfire ones,an emulator/translator in HW so to speak?
The emulator : my own emulator, it has to run from the internal SRAM of the coldfire. It uses self-modifying code.
Did you try if it is faster on 68060 optimized code than on average 68k code? From my understanding 060 optimised means less non implemented instructions, so the emulation only would be some kind of "pass through" for these instructions maybe giving more speed.
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Maybe I'm wrong, but the "newest" 040 of Freescale is 3.3 compliant (don't remember the exact production code), thus is up to 80MHz clockable.
Can it the useful to Minimig (ok, Maximig instead)?
I know there will be some issues with libraries (already fixed in the past years), but /me thinks it can be done.
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Donar wrote:
Did you try if it is faster on 68060 optimized code than on average 68k code? From my understanding 060 optimised means less non implemented instructions, so the emulation only would be some kind of "pass through" for these instructions maybe giving more speed.
It does not change anything, EVERY instructions are emulated by the emulator. The only impact on the emulator is the use of simple addressing mode vs. complex addressing mode.
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Donar wrote:
You could make it near native with a hardware translator.
You mean a device that translates 68k instructions to the appropriate Coldfire ones,an emulator/translator in HW so to speak?
Correct. It is actually the same trick used by both the AMD and Intel CPU's, translating through microcode from the more complex instruction set to a simplified internal one, only we'd be doing it via an external chip. The 68060 used such a system to it's proto-coldfire core, so much so that my college professor put that the coldfire was just the 060 w/ that translator removed.
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downix wrote:
.... The 68060 used such a system to it's proto-coldfire core, so much so that my college professor put that the coldfire was just the 060 w/ that translator removed.
I am trying to wrap my limited CPU knowledge mind around that statement. 68060 proto-coldfire core??? hmmmm .... I thought that the coldfire came out after the 68060 and it was a stripped down design with less instructions that met the embedded market demands of the time?
The term 68060 proto-coldfire core sounds to me (the average layman) like a part of the 68060 designed to copy a pre-existing coldfire CPU? Is this an Egg or the Chicken question, which came first, the 060 or the coldfire? I guess the coldfire could have as the 68000 series was on its way out and Macs were already moving to the PPC, which is why no Macs ever came from Apple with the 060 inside.
Sorry, just rambling to myself.
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It does not change anything, EVERY instructions are emulated by the emulator.
Yes, but for the say 75% percent of the instructions/adressing modes that match on 68060 and Coldfire would it be possible that the/an "emulator" just looks at an:
mov.l an decides to give a mov.l to the Coldfire, having "minimal" performance impact (say 20%)?
For an unimplemented instruction "Z" the emulator could instruct the Coldfire to do Instructions a+b+c giving "Z" thus having a (big) performance hit for these instructions.
I just wonder because Virtual Machines setting up fake CPU's seem to just work in that way (ok they can map every instruction 1:1). As they do not give a big performance hit when you emulate an 4 core system on your 2 core CPU.
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amigadave wrote:
downix wrote:
.... The 68060 used such a system to it's proto-coldfire core, so much so that my college professor put that the coldfire was just the 060 w/ that translator removed.
I am trying to wrap my limited CPU knowledge mind around that statement. 68060 proto-coldfire core??? hmmmm .... I thought that the coldfire came out after the 68060 and it was a stripped down design with less instructions that met the embedded market demands of the time?
The term 68060 proto-coldfire core sounds to me (the average layman) like a part of the 68060 designed to copy a pre-existing coldfire CPU? Is this an Egg or the Chicken question, which came first, the 060 or the coldfire? I guess the coldfire could have as the 68000 series was on its way out and Macs were already moving to the PPC, which is why no Macs ever came from Apple with the 060 inside.
Sorry, just rambling to myself.
Fundimentally, the 68060 uses a microcode-retranslation system paired up to a reduced-OPcode core, using hardware to translate the instructions that the core cannot natively run into ones that it can. The majority do just go through, but a few needed translating. This is how every high-speed CISC CPU has worked since the 68060. In the intel world the first was the NexGen 5x86, for example.
What my professor theorized was that despite PowerPC taking over the desktop arena, Mot had enough existing 68k customers to support that it turned an eye to how to advance the m68k without hurting it's new PowerPC strategy. The Motorola engineers basically removed this microcode stage from the m68060 and with a little work, viola, you have the Coldfire. That way, their performance customers, such as Apple, wouldn't be upset that Motorola was hurting their migration by releasing faster CPU's of the old-family, but Motorolas embedded customers would still get the product they needed.
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@downix,
Great explanation! (even for us laymen) :lol:
I guess I was mostly right in that the coldfire was a stripped down 060 for the embedded market.
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Hmmm, thinking out loud. Since the Coldfire had that hardware translator removed and since many have wanted to develop a Coldfire accel for the Amiga because of the Coldfire's low cost and availability, as well as its increased speed, maybe we could get Dennis to sit down for another year and develop the missing 68060 part of the Coldfire in an FPGA and we would end up with a real A3000/A4000 Coldfire accelerator that works and runs at 3 to 10 times faster than our old Phase5 060 boards?
If it were that simple, I guess someone would have done it already. :-?
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amigadave wrote:
Hmmm, thinking out loud. Since the Coldfire had that hardware translator removed and since many have wanted to develop a Coldfire accel for the Amiga because of the Coldfire's low cost and availability, as well as its increased speed, maybe we could get Dennis to sit down for another year and develop the missing 68060 part of the Coldfire in an FPGA and we would end up with a real A3000/A4000 Coldfire accelerator that works and runs at 3 to 10 times faster than our old Phase5 060 boards?
If it were that simple, I guess someone would have done it already. :-?
amigadave, couple of things:
1. Dennis has already done enough hard work for us on this project already. Anything else we get from him is a huge bonus IMO.
2. TobiFlex has already implemented a Minimig+68000 on FPGA. This solution isn't open source yet but hopefully it will be soon. An A500 wouldn't use the extra instructions of an 68060, right?
3. As we already have a 68000 on FPGA, we could easily overclock it an get some of the speed improvements you are looking for.
There would be two things that limited overclocking; the maximum speed of the FPGA and the clock speed of the Amiga (which we cannot change AFAIK). Some useful overclocking info on this website (http://members.iinet.net.au/~davem2/amiga.html):
"Firstly is the computer being modified of "synchronous" or "asynchonous" design? Synchronous is where the CPU is clocked at a speed which is a direct multiple of the main clock which runs the entire computer."
If the main A500 clock runs at approximately 7.14MHz, we should be able to overclock the 'processor' part of the FPGA to high speeds for an Amiga CPU if we stick to multiples of this base value (121.38MHz, 164.22MHz, etc...). Anyone know what the maximum clock speed for a Spartan-3 FPGA is?
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HenryCase wrote:
An A500 wouldn't use the extra instructions of an 68060, right?
Wrong.
If the program is compiled for / written for 68060 it will use any extra instructions.
If not, a standard 680x0 program will use the improved architecture, parallel execution units, Instruction and data cache, branch prediction etc.
If all you want to do is run A500 software, stick with MiniMig.
Also bare in mind that a LOT of Amiga workbench software is written for 68020+ only.
HenryCase wrote:
If the main A500 clock runs at approximately 7.14MHz, we should be able to overclock the 'processor' part of the FPGA to high speeds for an Amiga CPU if we stick to multiples of this base value (121.38MHz, 164.22MHz, etc...).
It doesnt work like that.
Anyone know what the maximum clock speed for a Spartan-3 FPGA is?
Absolutely doesnt work like that.
FPGA's dont really have a "maximum clock speed". Their maximum speed is determined partly by type/generation of FPGA it is and mainly by the logic that is programmed into them.
While the FPGA might be rated to 300MHz, when programmed it wont do a fraction of that speed!
Maybe low 10's of MHz with a well written design. Certainly not 100's.
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Alexh, thank you for that info.
alexh said:
"If not, a standard 680x0 program will use the improved architecture, parallel execution units, Instruction and data cache, branch prediction etc."
I'd like to break down that statement so I have a better chance of understanding it:
"Improved architecture". Are you referring to refinements to existing operations (i.e. streamlined instruction architecture) or the addition of new facilities (i.e. more data bandwidth)?
"Parallel execution units" How does the 68060 do this? I didn't think the 68K series CPUs were parallel processors in the modern sense. Did it have multiple ALUs/FPUs, more registers, bigger instruction pipelines?
"Instruction and data cache" Are you referring to the increased space for more complex operations (complex in the sense that the 68060 could do larger calculations in a smaller number of cycles)?
"Branch prediction" You've lost me there. How does this work?
alexh said:
"It doesnt work like that."
Care to explain why we wouldn't be able to 'overclock' the 68000 in the way I described? Surely all timing is set on the FPGA. What would 'overclocking' the 68000 code break in the Minimig?
alexh said:
"FPGA's dont really have a "maximum clock speed". Their maximum speed is determined partly by type/generation of FPGA it is and mainly by the logic that is programmed into them.
While the FPGA might be rated to 300MHz, when programmed it wont do a fraction of that speed!
Maybe low 10's of MHz with a well written design. Certainly not 100's."
I have heard this before, in my enthusiasm for the overclocking idea I forgot that the maximum speed of FPGAs is determined by the complexity of their design as well as FPGA type. My question is, what does that 300MHz rating even mean, how is it calculated?
Thanks in advance for your help.
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Hi to all,
Wow, this thread is hot... seems to be that everybody have a small poject on the Amiga based on Minimig.
I'm planning some stuff also, but as my time is getting very short, I don't want to make it public, as it may not see the light of the day (3 years old twin daughters and a classic car to restore fills my weekends :-D )
Let me share some of my opinions. Then you can throw me some rocks :-D. I really believe that if there is a future for the Amiga it is in our hands, as the "big companies" had proven to be such a disaster. There are a lot of other folks doing compatibles around the world, and Minimig is a great start.
I think if AGA compatibility is the target, we should have that in mind when doing any board. The hardware should be capable of supporting it, and we can grow the software slowly from OCS to ECS and then AGA without doing new boards. This keeps costs acceptable for us hobbists.
The 68060 is an expensive guy. Coldfire is cheaper, but a litle bit incompatible. I would go to PPC, as OS4 needs it, and it is cheaper than the 060, but I believe the best place to start is to seek A1200 compatibility, so use a 020 or a 030 as a plug in daghterboard. It helps to use processor development kits also.
Most software will run with AGA and 020. When we get A1200 compatibility, a PPC is the best choice to speed it up.
Virtex 4 is also expensive. You can get a cheaper set up with a MPC5200 and a Spartan3, and the MPC already has SDRAM/DDR controllers, Ethernet, USB and some stuff more.
I've talked with some friends who work with FPGAs, and they told me VHDL would fit best for this kind of project, althrough Verilog is easier to learn. I'm trying to learn Verilog first anyway.
Now two quick questions to the people who are playing with Minimig already: How many gates are we using from the Spartan ? I would like to know how big we could expect an AGA version to be...
The second one: wouldn't it be cheaper to use two or three smaller FPGAs for an AGA Minimig than upgrade to a bigger FPGA? The cost of those chips seems to grow exponentially.
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@HenryCase,
I was not thinking of just speeding up the MiniMig a little so games would run faster, or at the correct speed. I am thinking of future projects where people will be working on advanced Amiga compatible designs by using the work Dennis has started and forwarding it up to and beyond anything we currently have in hardware on Classic Amigas. This could include using 68060 CPUs, but it would be better if a Coldfire solution could be designed, as it is faster, cheaper and more available, and it is an extension of the 68000 series CPU. Another group will probably go in the direction of PPC CPUs to obtain compatibility with AmigaOS4.x and yet another group will move toward integration with x86 architectures to use AROS and take advantage of all the cheap hardware.
I think one of the next steps will be to have ECS and AGA recreation in hardware and then go beyond to what AAA would have been.
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AeroMan wrote:
I've talked with some friends who work with FPGAs, and they told me VHDL would fit best for this kind of project, althrough Verilog is easier to learn.
I dont know who you're mates are but they are either poor engineers or they make stuff up they dont know!
VHDL and Verilog are just languages, you can write exactly the same thing in both languages. They are equally supported in all Xilinx and Altera FPGA's tools and have been for a long time.
If anything VHDL got full support later than verilog due to it's extensive typing and features such as generate and records.
AeroMan wrote:
How many gates are we using from the Spartan ?
You should start thinking about SLICES and BLOCKRAM rather than gates. Gates is an ASIC metric. To know exactly how much MiniMig uses... try to Synthesis it. The Xilinx toolkit is available freely as is the MiniMig source.
http://www.amiga.org/forums/showthread.php?t=32604
AeroMan wrote:
I would like to know how big we could expect an AGA version to be...
Impossible metric to measure, even if you knew the current size of MiniMig. How long is a bit of string? You have no idea how much more complicated AGA is over OCS, or how well MiniMig is written or how well someone will write AGA.
AeroMan wrote:
The second one: wouldn't it be cheaper to use two or three smaller FPGAs for an AGA Minimig than upgrade to a bigger FPGA? The cost of those chips seems to grow exponentially.
Yes. Most designs (Prometheus, X-Surf, Mediator, Picasso IV) use multiple smaller FPGA's (CPLD's) rather than go to bigger ones. There is usually some cost / size boundary. However IMHO form-factor is a bit selling point of MiniMig. In fact to me, it's the only selling point.
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amigadave wrote:
@HenryCase,
I was not thinking of just speeding up the MiniMig a little so games would run faster, or at the correct speed. I am thinking of future projects where people will be working on advanced Amiga compatible designs by using the work Dennis has started and forwarding it up to and beyond anything we currently have in hardware on Classic Amigas. This could include using 68060 CPUs, but it would be better if a Coldfire solution could be designed, as it is faster, cheaper and more available, and it is an extension of the 68000 series CPU. Another group will probably go in the direction of PPC CPUs to obtain compatibility with AmigaOS4.x and yet another group will move toward integration with x86 architectures to use AROS and take advantage of all the cheap hardware.
I think one of the next steps will be to have ECS and AGA recreation in hardware and then go beyond to what AAA would have been.
amigadave, you made a very good point by illustrating the different ways the Amiga community will want to take the Minimig. As I wasn't considering all the possibilities when I made my comments about your previous post I didn't give your ideas fair consideration and for this I apologise.
I don't have a problem with any ideas for Minimig expansions, the more options we have the better the project as a whole becomes. However, I am concerned with making sure the Minimig is improved as fast as possible to make it a viable source of new Amiga hardware rather than making it a bit of a curio. For the amount of work necessary to make these big hardware improvements I tend to see the PPC route as the one with the most immediate potential. When the hardware is sufficiently powerful then we have more time to explore other uses of the tech. IMHO.
AeroMan wrote:
I think if AGA compatibility is the target, we should have that in mind when doing any board. The hardware should be capable of supporting it, and we can grow the software slowly from OCS to ECS and then AGA without doing new boards. This keeps costs acceptable for us hobbists.
Aeroman, this is very important, and it's something that hasn't been discussed much. The key to doing this is expandibility, which is the one major weakness with the v1.1 PCB. Let's say an AGA solution was made. It seems very likely that AGA wouldn't fit on the current design, so those people who want it have no choice but to upgrade to a newer PCB revision. If we had something like the CPU Fast Slot then we could design an upgrade board for the existing design, with an FPGA providing the extra processing capacity. People who hadn't bought a Minimig before this time could just buy a newer version of the PCB with the expanded capabilities built in.
I don't know if Minimig v1.1 had enough I/O pins on the FPGA to handle an expansion port, but if TobiFlex does release his code then we'll have plenty more I/O pins to play with. Downix, how many pins does your A500-like expansion port need?
If an expansion port is included in v1.2 a greater number of early adopters have more versatile hardware sooner, which in turn will speed up development. Any thoughts?
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I think there's more to having AGA support than just changing the Verilog. It'll need the data and probably address buses upgrading to 32bit as well as running at a higher clock speed. Then to actually support software which expects AGA you'll probably need at least an '020 processor.
Basically take the A1200 as a minimum spec' for AGA and upgrade the MiniMig v1.1 to it.
From the way I've just written it that doesn't actually sound like too onerous a task :-D but I bet in practice it won't be so simple!
There seems to be a fairly common theme in peoples postsa bout AGA probably not fitting into the current FGPA which I'm curious about. I seem to remember Dennis stating that he was only using about 60% of the current for OCS. Now the difference between OCS and AGA wasn't that staggering, a faster and wider data bus. Extra registers etc, but it was mostly described as evolutionary rather than revolutionary.
What I'm trying to say is that I've heard no good argument as to why AGA shouldn't fit within the current FPGA. Has anyone got any knowledge about this? It seems to be a bit of an inaccurate science guessing how much space any given implementation might occupy.
Also a CPU fast slot isn't going to make a v1.2 any better at supporting AGA as it'll still be connecting to the same FPGA via the same 16bit wide data path running at half the clock speed of AGA. Since a large part of AGAs benefit was actually the 32bit data bus and the doubled bus clockspeed over the OCS/ECS system you'll lose whatever benefits you hope to gain by having it.
Just my opinion obviously.
Andy
HenryCase wrote:
AeroMan wrote:
I think if AGA compatibility is the target, we should have that in mind when doing any board. The hardware should be capable of supporting it, and we can grow the software slowly from OCS to ECS and then AGA without doing new boards. This keeps costs acceptable for us hobbists.
Aeroman, this is very important, and it's something that hasn't been discussed much. The key to doing this is expandibility, which is the one major weakness with the v1.1 PCB. Let's say an AGA solution was made. It seems very likely that AGA wouldn't fit on the current design, so those people who want it have no choice but to upgrade to a newer PCB revision. If we had something like the CPU Fast Slot then we could design an upgrade board for the existing design, with an FPGA providing the extra processing capacity. People who hadn't bought a Minimig before this time could just buy a newer version of the PCB with the expanded capabilities built in.
I don't know if Minimig v1.1 had enough I/O pins on the FPGA to handle an expansion port, but if TobiFlex does release his code then we'll have plenty more I/O pins to play with. Downix, how many pins does your A500-like expansion port need?
If an expansion port is included in v1.2 a greater number of early adopters have more versatile hardware sooner, which in turn will speed up development. Any thoughts?
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alexh wrote:
I dont know who you're mates are but they are either poor engineers or they make stuff up they dont know!
VHDL and Verilog are just languages, you can write exactly the same thing in both languages.
I'm not stating that we should ignore what was done in Verilog and try to rewrite everything in VHDL. It was just one comment from them I would like to share.
Actually, one of them is PHD... What they told me in that discussion is that there are some stuff that you can implement in VHDL easier than in Verilog, but it is more difficult to learn. I'm starting to learn those languages right now, so I don't have enough knowledge to say if it is true or not, but it sounds reasonable to me, as Assembly and C are also languages and althrough C is very powerful, there are things that can't be done using it. You can do everything in Assembly, but it is way more difficult.
alexh wrote:
Impossible metric to measure, even if you knew the current size of MiniMig
Yes, It can give me a north to go. With the 60% number that AJCopland said below, I can tell the hardware needs prevision for a second FPGA or a bigger one, but it may fit in the current chip. Why? Because Paula and the CIAs are the same, blitter and copper have little differences, and the big work will be on Lisa and the memory fetch part of Alice. If the number was 30%, for example, I would say 99% of chance that if there are enough free IOs, we can use the same chip.
alexh wrote:
However IMHO form-factor is a bit selling point of MiniMig. In fact to me, it's the only selling point.
I agree with you, if we consider the Mini side fo Minimig. But if we are heading to a new Amiga hardware, we will need more area for stuff. The A1200 and A500 have perfect sizes, but a PC sized board would be nice, as we could fit it inside cheap PC cases.
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AJCopland wrote:
I think there's more to having AGA support than just changing the Verilog. It'll need the data and probably address buses upgrading to 32bit as well as running at a higher clock speed. Then to actually support software which expects AGA you'll probably need at least an '020 processor.
AJCopland, I agree about the 68020 requirement for AGA Amigas, but would argue that this is even more reason to have two FPGAs. I'd certainly prefer 2x FPGAs than 1x FPGA and 1x 68020, simply because this is a more flexible design and frees us from components that may not be supported forever.
Also a CPU fast slot isn't going to make a v1.2 any better at supporting AGA as it'll still be connecting to the same FPGA via the same 16bit wide data path running at half the clock speed of AGA. Since a large part of AGAs benefit was actually the 32bit data bus and the doubled bus clockspeed over the OCS/ECS system you'll lose whatever benefits you hope to gain by having it.
Just my opinion obviously.
Andy
I'm just trying to make sure the Minimig is good VFM (at least as much as possible) by ensuring we think about features the design may need in the future, rather than designing a new board that will hinder growth. Would a CPU Fast Slot really not help AGA? Using my limited knowledge, I figure since the slot is 86pin it could handle a 32bit data bus. I could be wrong.
AJCopland said:
Basically take the A1200 as a minimum spec' for AGA and upgrade the MiniMig v1.1 to it.
I like this idea.
I would just like to state that there's plenty of mileage left in the v1.1 design for improvements (ability to write to the MultiMediaCard being #1 in my opinion), but the next revision of the PCB should be more ambitious.
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HenryCase wrote:
Downix, how many pins does your A500-like expansion port need?
92, but I wasn't using "pins" but a card-edge.
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Just want to point out that Xilinx Spartan-3 (like XC3S400 and XC3S500E) can do 622 Mbps transfers via a single I/O. So a 2x FPGA board won't need a staggering amount of fpga2fpga lanes.
Regarding Coldfire, it might be fast enough and have other benefits. But will it be cycle accurate to the MC68060 ..?, because lot of Amiga software is relying on cycle exact timing.
Cycle exact timing is the reason why FPGA/CPLD will perform and UAE won't.
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downix wrote:
HenryCase wrote:
Downix, how many pins does your A500-like expansion port need?
92, but I wasn't using "pins" but a card-edge.
92, a fair few then! :crazy: :-D
I should have asked a little clearer, but I was actually wanting to know how many I/O pins from the FPGA (or 68000 CPU) your design uses. Could you break that down for me?
freqmax wrote:
Just want to point out that Xilinx Spartan-3 (like XC3S400 and XC3S500E) can do 622 Mbps transfers via a single I/O. So a 2x FPGA board won't need a staggering amount of fpga2fpga lanes.
Awesome, I was hoping this was the case. Is the transfer speed affected by FPGA complexity?
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HenryCase wrote:
downix wrote:
HenryCase wrote:
Downix, how many pins does your A500-like expansion port need?
92, but I wasn't using "pins" but a card-edge.
92, a fair few then! :crazy: :-D
I should have asked a little clearer, but I was actually wanting to know how many I/O pins from the FPGA (or 68000 CPU) your design uses. Could you break that down for me?
2 pins total. Everything else is off of the CPU bus.
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The 622 Mbps speed depend on how you design your data flows.
I think every flip-flop in Spartan-3 cause a delay about 5 ns.
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AeroMan wrote:
I'm not stating that we should ignore what was done in Verilog and try to rewrite everything in VHDL. It was just one comment from them I would like to share.
Sure, but the comment is invalid.
AeroMan wrote:
Actually, one of them is PHD... What they told me in that discussion is that there are some stuff that you can implement in VHDL easier than in Verilog
Not true. Trust me I've worked as a Verilog and VHDL designer for over 10 years. Ask them to name something, just out of curiosity.
AeroMan wrote:
but it is more difficult to learn.
It depends. If you've never done C (software) then you'll find both equally difficult. If you've done any C then you'll probably favour verilog as its syntax is quite similar.
AeroMan wrote:
as Assembly and C are also languages and althrough C is very powerful, there are things that can't be done using it. You can do everything in Assembly, but it is way more difficult.
Nice simile. Unfortunately not a valid one. C is a high level language and Assembler is a low level language. VHDL and Verilog are both equally high level languages.
Verilog has pro's and cons, VHDL has pro's and cons. The majority are not valid for MiniMig as they centre on verification and code reuse.
AeroMan wrote:
With the 60% number that AJCopland said below, I can tell the hardware needs prevision for a second FPGA or a bigger one.
No you cant, cos you dont know how more complex AGA is over ECS. Dont try to tell me you do, cos you dont :-P
The only thing you could work out is if we had enough I/O for 32-bit CPU/RAM interface and 24-bit video interface.
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What's the status of the Softcore MC68000 eg Suska, and opencore.org ..?
Does it work long enough to at least show workbench screen?
If it works good enough. Then we have a starting point for a build that don't require massive parallel pcb traces.
(Obviously the DE2 build has something going)
Then there's the mc68060 softcore.. :-D
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downix wrote:
92, but I wasn't using "pins" but a card-edge.
If you don't mind me asking what kind of connector are you using? One of the MCA style edge connectors like the ones on the CD32 or one that matches the original A500 more closely?
I was thinking that if you're making a connector design then it's not going to be readily usable by the old A500 expansions due to the 3.3v and 5v issues. So why not make it using a more common and easy to source connector type?
Andy
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AJCopland wrote:
downix wrote:
92, but I wasn't using "pins" but a card-edge.
If you don't mind me asking what kind of connector are you using? One of the MCA style edge connectors like the ones on the CD32 or one that matches the original A500 more closely?
I was thinking that if you're making a connector design then it's not going to be readily usable by the old A500 expansions due to the 3.3v and 5v issues. So why not make it using a more common and easy to source connector type?
Andy
I have been considering just this. The slot is 3.3v, but my thinking was to also make an adaptor to turn it into a 5v A500-slot clone. But first things first, need to find something of at least 92-pins for a connector. (I need it a lot smaller than the A500's slot to work)
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Some developer boards (Digilent) use "Hirose FX2" connectors I think. These could be used?
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freqmax wrote:
Some developer boards (Digilent) use "Hirose FX2" connectors I think. These could be used?
They could, yes. TYVM