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Amiga computer related discussion => Amiga Hardware Issues and discussion => Topic started by: ThomasML on September 04, 2007, 12:13:29 AM
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I'm making a new PCB layout based on the v1.1 schematics, and I'm wondering how many would be interested in this. My plan for the design is this:
* Add the slightly larger BGA-version of the FPGA (173 IO pins instead of 141).
* Make the board be 12cm x 12cm (to meet nano-itx requirements)
* Equip the board with pinout headers instead of the various connectors to make it easier to adapt to any casing.
I'm still asking around at various PCB manufacturers for pricing on manufacturing and assembly, so I don't know any price yet, I'm hoping to have it by the end of the week, or early next week.
So the part where I need feedback (in privmsg, I would prefer):
* How many assembled boards do you want?
* Do you want a kit with pinout -> connector for all the connectors that's on the current minimig-design? (I'm trying to figure out if enough people want this to make it part of the package I should send off to the factory)
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Thomas
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I just want an assembled Minimig board. I'm prepared to build my own case, but that's about it. It's a nice idea to have the ports connect to pins so that they can be positioned by the user in whatever case they either buy or build, but I'm not particularly bothered.
Whoever produces the first assembled models for sale will get an order from me. I'm probably going to need 3 Minimigs: 1 for me and 2 for the kids. Of course, I could pass "mine" onto the kids if I end up upgrading to a more advanced Minimig design.
Good luck with your project.
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Depending on the price I might be interested in purchasing a board.
PM has been sent.
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you have my support, if you need help say it.
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Hi Thomas,
I want one assembled board with whatever connector options is easiest for you to deliver.
Fester
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Seeing as you're making it nano-itx size, you might want to have a look if there are any standard nano-itx connector layouts you could use. With mini-itx there are standard layouts (or at least a standard backplate area that you can use). If you do go completely the pin header route, please use the standard pin header layouts for things such as the serial port; it'll make connecting them up so much easier.
Hans
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Couple of questions:
What will you do with the unused pins, bring them to an empty header/pin array for expansion?
Are there any other differences between the BGA and QFP versions of the FPGA?
Andy
PS: I'd also be interested in an assembled one, have already said I'd take at least one blank board from Xenepp so will honour that request as well.
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Hans_ wrote:
Seeing as you're making it nano-itx size, you might want to have a look if there are any standard nano-itx connector layouts you could use. With mini-itx there are standard layouts (or at least a standard backplate area that you can use). If you do go completely the pin header route, please use the standard pin header layouts for things such as the serial port; it'll make connecting them up so much easier.
There's hard to find any white papers about the Nano-itx. Via has white papers on mini-itx and pico-itx, but nothing on nano-itx, so I've looked at motherboard documents to see where the mounting holes needs to be. I'm definitely going down the pinheader route, so no need to worry about matching the backplate, and I'm also going to use standard layouts for the serial-ports, for instance.
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Thomas
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AJCopland wrote:
Couple of questions:
What will you do with the unused pins, bring them to an empty header/pin array for expansion?
Yes, I'll route them to a pinheader array so that they can be used for whatever people like.
Are there any other differences between the BGA and QFP versions of the FPGA?
Not much besides more IO-pins and some extra dollars in cost, no.
[/quote]
PS: I'd also be interested in an assembled one, have already said I'd take at least one blank board from Xenepp so will honour that request as well.
[/quote]
This is why I was a bit reluctant to announce this, I wanted to get feedback from Xenepp first, to make sure he didn't end up with a large batch of blank boards. But, I haven't heard anything from him yet, I am afraid :-(
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Thomas
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I would be interested in an assembled board, with any connector options (although I like the idea of an ATX-style backplane.)
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Great idea, but uhm...
Make the board be 12cm x 12cm
...isn't the original Minimig board already that size? http://en.wikipedia.org/wiki/Minimig (http://en.wikipedia.org/wiki/Minimig) :-?
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I might be interested based on cost. I already have an order with Xenepp, so, price will be a factor. The v1.1 from Xenepp will get me started, but the added expandability of the larger BGA has interest for future updates. I wouldn't be entirely against buying one if a larger run would reduce the manufacturing cost, so that those that will be doing updates can more easily afford them.
I do think it would be a good idea if a model naming scheme could be implemented so that we could easily keep track of what is what.
I started a MiniMig Model Name thread (http://www.amiga.org/forums/showthread.php?t=31222)
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ThomasML wrote:
AJCopland wrote:
PS: I'd also be interested in an assembled one, have already said I'd take at least one blank board from Xenepp so will honour that request as well.
This is why I was a bit reluctant to announce this, I wanted to get feedback from Xenepp first, to make sure he didn't end up with a large batch of blank boards. But, I haven't heard anything from him yet, I am afraid :-(
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Thomas
Don't worry I'm still going to get one of those bare boards from Xenepp like I said :-D However I suspect I'll be buying many variants of the MiniMig over the coming years!
The bare board will allow me to choose components and to build one myself, however one using a larger BGA version like yours would be best pre-assembled as I can't do BGA myself.
Andy
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I have on eon order with Xenepp but still might be insterested in at least one other. But would like to know price first.
Thanks
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Hi,
I would be interested in an assembled board. I am ok with the original design since it's part of the fun to make a custom case for it.
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Per-Erik
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@ThomasML:
I think you have to measure some existing Nano-ITX board :-)
(when via.com documentation is so nonexistant)
There are infact two "standard" layouts for the serial-ports (DE9).
Maybe we could arrange the RAM_xx signals in order for the v1.1 board aswell?
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i'm interested in one.
I use FPGAs at work, and it'd be neat to have those extra IO pins available on a header, so that other peripherals can be made for it (framegrabbers and such) or perhaps parallel port, floppy port, etc.
What kind of price point are you looking at for the board/kit/package?
I think i would prefer all of the io connectors on headers, but i'd be fine with on-board connectors
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Put me down for one, depending upon price. PM sent.
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Why not go with an XC3S500E instead of the 3S400? It's cheaper, has more logic cells and is newer, so probably available longer.
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freqmax wrote:
@ThomasML:
I think you have to measure some existing Nano-ITX board :-)
(when via.com documentation is so nonexistant)
There are infact two "standard" layouts for the serial-ports (DE9).
I'm leaning more and more towards using pinouts on the board, actually. This will be the most flexible option (make two diff. layouts is too expensive :-( )
Maybe we could arrange the RAM_xx signals in order for the v1.1 board aswell?
Anything special you have in mind?
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Thomas
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@ThomasML:
I don't suggest making two versions. Just that you pay attention to which PinHead<->DE9 wiring scheme you will use.
As for the RAM_xx signals, just look at the current wiring:
http://www.opencircuits.com/Minimig_Board_v1.0_FPGA_connections
I think that if the signals are A0, A1, A2, A3 etc.. routing will be much easier and electrically sound.
If you go for the BGA route. I suggest you have the pcb board DRC checked at fab. And the FPGA-BGA assembled aswell at fab. However the rest people could do by themselfes.
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Mikkel wrote:
Why not go with an XC3S500E instead of the 3S400? It's cheaper, has more logic cells and is newer, so probably available longer.
Unless the 3E is missing some features that the 3 has, and that's used by the Minimig, I don't see any reason not to choose the XC3S500E for the design. Good catch :-)
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Thomas
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freqmax wrote:
@ThomasML:
I don't suggest making two version. Just that you pay attention to which PinHead<->DE9 wiring scheme you will use.
Ok
As for the RAM_xx signals, just look at the current wiring:
http://www.opencircuits.com/Minimig_Board_v1.0_FPGA_connections
I think that if the signals are A0, A1, A2, A3 etc.. routing will be much easier and electrically sound.
You're thinking about where the RAM-signals physically connects to the FPGA-package?
If you go for the BGA route. I suggest you have the pcb board DRC checked at fab. And the FPGA-BGA assembled aswell at fab. However the rest people could do by themselfes.
My plan was to get pricing on the fully assembled board (and that includes checking, but I'll get a quote for only assembling the BGA-package as well, but I think most people would want a fully assembled board).
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Thomas
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ThomasML wrote:
but I think most people would want a fully assembled board.
How very true. Although there are quite some people who are not really afraid to do some basic soldering, I think the majority is pretty much "solderingly challenged" (just like me).
I very much would like to have a fully-assembled Minimig, no matter the size, as long as it works :-)
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ThomasML wrote:
You're thinking about where the RAM-signals physically connects to the FPGA-package?
Yes.
Less vias => cleaner design => less emi etc..
And easier to track wires if the need arise.
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McVenco wrote:
ThomasML wrote:
but I think most people would want a fully assembled board.
How very true. Although there are quite some people who are not really afraid to do some basic soldering, I think the majority is pretty much "solderingly challenged" (just like me).
Soldering a BGA isn't some basic soldering. AFAIK, it's impossible to do with a soldering iron; you need the right equipment to do it.
Hans
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You cannot solder a BGA with a soldering iron, you need reflow oven. Prices start at about £150 and go up.
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alexh wrote:
You cannot solder a BGA with a soldering iron, you need reflow oven. Prices start at about £150 and go up.
Or you could reflow in a nice toaster oven, but thats for us hackjobs (:
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koaftder wrote:
alexh wrote:
You cannot solder a BGA with a soldering iron, you need reflow oven. Prices start at about £150 and go up.
Or you could reflow in a nice toaster oven, but thats for us hackjobs (:
Which is the technique that I'd use, if I had an oven set up for it. I'd be interested to hear of any "hackjob" method of verifying that all the solder balls are correctly soldered; you can't exactly inspect them visually.
@ThomasML
Are you considering putting a proper 24-bit RGB DAC on the board for video? I'd definitely be interested in the board if it included that. Such a feature would provide make adding AGA support a possibility. That would mean a certain amount of extra work though.
EDIT: Adding 24-bit RGB would be pointless without a 68020+ processor, so it's probably too much work for now, particularly as you're using the v1.1 schematics.
Hans
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OK, maybe this is a stupid idea, but what about having the BGA FPGA put onto a daughter card, so that other revisions of the MiniMig could use the same FPGA without the BGA worries? Are the electrical tolerances to tight for that? :crazy:
Of course I certainly don't want to discourage a run of fully factory assembled MiniMigs! :-D
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Belial6 wrote:
OK, maybe this is a stupid idea, but what about having the BGA FPGA put onto a daughter card, so that other revisions of the MiniMig could use the same FPGA without the BGA worries? Are the electrical tolerances to tight for that? :crazy:
I'm not going to put the FPGA on a sep. card, no, that would be to expensive, I'm afraid.
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Thomas
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Is it only a cost issue, or is there a technical reason?
I do understand that cost matters, so I'm not trying to persuade you to change your mind.
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Belial6 wrote:
Is it only a cost issue, or is there a technical reason?
I do understand that cost matters, so I'm not trying to persuade you to change your mind.
It's perfectly doable to stack FPGAs, and I'm looking at adding a set of connectors to be able to connect more FPGAs to the design by making daughter-cards with the right set of connectors.
But making such cards is on of the tasks that should be on the todo-list, rather than on the "to get it working in the first place"-list.
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Thomas
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@Hans_:
Reflow oven:
* http://dlharmon.com/solder/smd.html
* http://www.seattlerobotics.org/encoder/200006/oven_art.htm
* http://www.elektor.com/magazines/2006/january/smd-reflow-soldering-oven.58007.lynkx
* http://openhardware.net/Misc_Stuff/ToasterSMD/
Why is 68020+ needed for 24bit RGB?, dram speed have improved speed since Amiga
days, if that's the bottleneck.
Also many monitors have a hard time to make use of 24bit over analog transmission afaik. DVI or HDMI would proberbly be more suited for such high colour dynamic.
@Belial6:
How should the FPGAs cooperate?
Better to have one large FPGA. Only needs a rerun of Webpack P&R anyway. If the m68k is included in the source code anyway. Or to add/remove extra i/o capabilities.
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freqmax wrote:
@Hans_:
Why is 68020+ needed for 24bit RGB?, dram speed have improved speed since Amiga
days, if that's the bottleneck.
Not needed, but AGA is 32-bit and the 68000 has a 16-bit external bus.
Hans
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@freqmax:
I think there is some confusion. In never suggested a second FPGA. That was suggested by ThomasML. I was just asking if there was a technical reason to have any FPGA soldered directly on the board. It seems that it is only a cost issue.
My original thought was that since the BGA package of the larger, more powerful FPGAs is the biggest limiting factor on some of the enhancements some people are considering, maybe having a board with nothing but the FPGA and a connector would make sense. This would allow larger more powerful FPGAs to be used in multiple designs, without every hardware revision having to be factory assembled.
ThomasML implied that this would be cost prohibitive. Thus answering my question. He also added that he is considering at a later date, working on a slot to add a second FPGA. While this was not an answer to the question I was asking, it was interesting none the less.
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@Hans_:
Maybe I should ask like this, is it due memory bus speed or some other issue that a 32-bit bus is needed?
@Belial6:
Enterpoint have an assembled FPGA+32M SDram on a PGA socket header. This would allow FPGA upgrade at will. (cost 110E)
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freqmax wrote:
@Hans_:
Maybe I should ask like this, is it due memory bus speed or some other issue that a 32-bit bus is needed?
Basically all AGA software was designed for a machine with a 32-bit bus and a minimum 68EC020 processor running at ~28MHz. A 16-bit bus means half the memory bandwidth, and a slower processor will just make things worse. I'd expect most AGA games to fail to work properly on anything less than the basic A1200 specs.
Hans
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@Hans_:
The memory bandwidth of Minimig is artificially throttled (according to Dennis). So it should be possible to use the full bandwidth of the ram to feed the AGA graphics.
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Ï want one. :-D
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@freqmax
freqmax wrote:
@Hans_:
The memory bandwidth of Minimig is artificially throttled (according to Dennis). So it should be possible to use the full bandwidth of the ram to feed the AGA graphics.
It's the bandwidth between the CPU and the chipset that's the problem, not the chipset and memory. The timing of the CPU's bus is limited by the CPU. You could get the AGA chipset working, but performance would be substandard because the CPU is slow and it's memory bandwidth too limited.
Hans
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freqmax wrote:
Yes.
Less vias => cleaner design => less emi etc..
And easier to track wires if the need arise.
This is how I'm suggesting that the layout will be:
(http://langaas.org/images/fpga_layout_screenshot.jpg)
Feel free to comment :)
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Thomas
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Did you rebuild the MiniMIG Xilinx ISE Project with the new Spartan3E part/BGA package to make sure that new pin out would route (i.e. is the resulting pinout from Xilinx ISE floor planner)?
Also, please see Xilinx Spartan3/3E APP notes on BGA 4/6layer PCB and on SSO (Simultaneous switched outputs).
http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?iLanguageID=1&category=Publications/FPGA+Device+Families/Spartan-3E/Application+Notes
Check Xilinx XAPP689.pdf
Check Xilinx Xapp489.pdf
:-)
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lol well i can't comment on the technical side of it but it looks like all the main blocks I can identify are there. You'll have 10 user_io pins left. All 16 of the CPU address and data lines, likewise for the ram.
After that it all starts to look like a complicated game of scrabble :-D
Andy
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jkonstan wrote:
Did you rebuild the MiniMIG Xilinx ISE Project with the new Spartan3E part/BGA package to make sure that new pin out would route (i.e. is the resulting pinout from Xilinx ISE floor planner)?
No, I'm pretty sure it'll route well, but I'm about to install ISE and compile it now. Will let you know if there's any suggested changes from ISE.
The FPGA I've chosen has 1200k gates, tho, so it's a bit bigger than the one on the minimig today. It's also large enough to fit a 68k inside the fpga.
Also, please see Xilinx Spartan3/3E APP notes on BGA 4/6layer PCB and on SSO (Simultaneous switched outputs).
http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?iLanguageID=1&category=Publications/FPGA+Device+Families/Spartan-3E/Application+Notes
Check Xilinx XAPP689.pdf
Check Xilinx Xapp489.pdf
Yeah, I'll make sure to read those when I'm done with the schematics and starting on the pcb-layout. I've been altering a few things more than once lately, as I've been talking to Dennis on email and getting a few ideas here and there :-)
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Thomas
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AJCopland wrote:
lol well i can't comment on the technical side of it but it looks like all the main blocks I can identify are there. You'll have 10 user_io pins left. All 16 of the CPU address and data lines, likewise for the ram.
Actually, there's 10 user input-pins left, and 38 user input/output-pins left. So, a total of 48 pins left for fun and expansion.
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Thomas
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Thomas,
Please connect the MC68SEC000 Berr* pin12 to one of those FPGA pins.
:-)
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jkonstan wrote:
Thomas,
Please connect the MC68SEC000 Berr* pin12 to one of those FPGA pins.
That's marked as VCC in the schematics I have. Is that an error? Should it be on one of the Input (or Input/Output) pins from the FPGA?
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Thomas
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Thomas,
Please see this Open Circuits MiniMIG link where I explain why Berr* would be a nice to add back into the design.
http://www.opencircuits.com/Minimig_68K_CPU_BERR%2A_Support
:-)
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jkonstan wrote:
Thomas,
Please see this Open Circuits MiniMIG link where I explain why Berr* would be a nice to add back into the design.
Ok, I'll add map it, it's not like we're running out of pins or anything :-)
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Thomas
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Hi all
This is so cool! This very much reminds me of why I got into the Amiga to begin with :-)
Anyway, since the new FPGA has so many gates, are there enough for, say, an 020 or even 030 CPU in there? I mean, if you're making a whole new 'classic' Amiga then would it be too complex to make it an accelerated one? Even WB1.3 runs fine on an 030. I'll buy one regardless, but I'm just blue skying here. Is a faster CPU possible? Or do you just physically install one instead?
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Whilst 020 or 030 would be nice for a later revision I think this particular v1.1 revision is just to give us more pins to do things with from an expansion point of view. Though it is ThomasML whos doing the work on this version so he'd have a better idea.
Also adding an 020 or 030 has been discussed and seems like a major redesign of the board for a seemingly large number of reasons. Everything from voltages through clock speeds via board trace layouts etc and a bunch more stuff I didn't understand ;-)
Andy
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Tron2k2 wrote:
Anyway, since the new FPGA has so many gates, are there enough for, say, an 020 or even 030 CPU in there?
Someone's looking into that.... I believe the open-source 680x0 core has some problems. Another interesting idea- put the PIC controller in the FPGA. That would save a chip... but then you'd have to add a flash ram to load the FPGA.
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While doing BGA, a switch to DRAM would also make ram cheaper and larger.
With DRAM use + HDL cpu an ordinary pre-assembled 200 USD board can be used..
@JimS:
Putting the MCU (pic18) inside the FPGA poses an interesting chicken-and-egg problem. It will make upgrading the FPGA flash more cumbersome. And soldered EEPROMs have a limited number of write cycles.
The EEPROM loads the FPGA. And the FPGA can then read the flashcard. But it can't reload itself.
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freqmax wrote:
While doing BGA, a switch to DRAM would also make ram cheaper and larger.
With DRAM use + HDL cpu an ordinary pre-assembled 200 USD board can be used..
What kind of pre-assembled board are you talking about now? You mean we could use any of the starter kits instead of doing a custom board? Or, are you thinking that one could use the starter kits if one doesn't want to buy a custom board?
I also found flaws in my fpga pinout, I was missing some pins, so I've floorplanned it inside ISE now. Will publish the new suggested floorplan tomorrow.
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Thomas
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Yes, one could use pre-assembled ready to use developer boards. The only major obstacles is the physical CPU & Static-RAM.
VGA, Keyboard, means to load software, user i/o etc.. Is already there. I found XC3S1200 for 300 USD at digilentinc and XC3S1000 for 200 USD at xess.
This was my initial idea of an A500 implementation in FPGA. No need for special purpose boards.
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freqmax wrote:
Yes, one could use pre-assembled ready to use developer boards. The only major obstacles is the physical CPU & Static-RAM.
They're larger and contain stuff you probably don't need tho, but it would serve a purpose of course. In the end I think one would want custom boards tho, to be able to make the device smaller or just have all the cool stuff developed along the way, on one board.
But right now, we don't have anything besides a few schematics and nothing for mainstream to play with. And the boards you're talking about is a bit more pricey than most people would like, I think. (I'm not most people, I've already got digilents V2Pro-board :-D ).
So, what do you suggest we do? I don't need to continue this work if it's not needed (don't take this the wrong way). What one could do, is to make the board like it's now, with the extra user io-pins and everything, and continue developing the soft 68k and adding dram as an expansion. Some day down the line one would maybe end up with a working solution, but right now we only have the proven minimig-design that works. And we all know there's other work to be done to it, besides just the cpu and ram.
Any thoughts? :-)
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Thomas
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If I had to base all work on one fpga all-in-one board I think Enterpoint's Darnaw1 would be suitable. Its small, it can be used on 2 layer boards with 110 I/Os and on a 4 layer board 219, it has a 1200k gate Xilinx fpga and some RAM. No unwanted extras really. Initially you would have to make a 'motherboard' to plug it into with CPU, SRAM and PIC and regular ports but over time you can cut it down to just the ports, the rest is on the fpga.
1.2M gates should be well and truly enough space for whatever we can come up with - The main issue is price.
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@ThomasML:
They may be large and contain stuff you don't need. But they are working out-of-the-box for those that lack soldering skills. But have programming skills.
I think a custom board is excellent, but one doesn't have to require that everyone must have one to even get started.
I suggest we move to Dynamic RAM and make the HDL code compatible with the soft m68k code with high priority (Bonus is at least 32M ram!).
@Fantoma:
Darnaw1 have onboard 16 MByte DRAM, CPU can be simulated with soft m68k core and MCU (pic18) can be coded as HDL. Though some upgrade issues may arise.
@all:
Having all the critical stuff in one premade board eliminates many EMI issues aswell.
The Webpack have builtin DDR controller and opencores.org should have support for anything older. Then adding 68k core. One will have to initially put in checks and debug the code to make it start I presume.
It's also possible to use some of the blockram in Xilinx FPGA to debug the m68k core first. And then turn to debugging Dynamic ram. The distributed ram +
blockram in XC3S1600E is 109 kByte. This would allow using the parts of kickstart as test code. And then go ahead with Dynamic RAM support on a plain developer board.
Also keep in mind that Xilinx Webpack supports upto XC3S1500 and XC3S1600E. After that you have to pay for the P&R tool.
The real bottom line with this is that we will get many more developers on Minimig. So that other issues will be resolved faster. So any coding towards DRAM + soft CPU will help other issues implicitly.
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Ok, new layout, this time I've used ISEs floorplanning tool, and I've also done synthesis and bitfile generation.
(http://langaas.org/images/fpga_layout_screenshot_ISE.jpg)
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freqmax wrote:
Putting the MCU (pic18) inside the FPGA poses an interesting chicken-and-egg problem. It will make upgrading the FPGA flash more cumbersome. And soldered EEPROMs have a limited number of write cycles.
The EEPROM loads the FPGA. And the FPGA can then read the flashcard. But it can't reload itself.
Yeah, a which came first situation indeed. But, if you use one of those FPGA dev boards like the XESS one you mentioned later, the flash ram is already present. The XESS board can store 4 fpga bitmaps. So it should be possible to configure the FPGA without the pic, and reserve a vhdl pic for just floppy emulation and the control panel.
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Regarding that XESS XSA-3S1000. Maybe the CPLD could replace the pic?, and software loaded via the DB25 parallell port?
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There's one possible project with a large BGA FPGA. Adding an m68k cpu. And then construct HDL code that will compare the signals of a real cpu and a HDL version.
That would allow development and improvement of such HDL m68k cpu.