It doesn't matter to me how certain you think you are about how Dennis went about cloning the A500 and creating MiniMig. What does actually really matter to me is that you have your facts all mixed up. Dennis has in fact been cloning the A500 chip-by-chip. If you do not believe me, please feel free to read the 850+ posts in the "Amiga in an FPGA: MiniMig" forum topic OR even contact Dennis on the subject.
Funny, I've been following that thread and I don't recall anything saying that he's been cloning it chip by chip. Sure, he started with the copper coprocessor (which is NOT a chip in it's own right but a sub-component) and then moved to other parts such as the blitter system. That's the only way to do a project like this. I don't have my facts mixed up at all. Dennis van Weeren has taken an overall behavioural approach. Of course he's implemented each sub-component one-by-one. Just not chip-by-chip. Why would he bother to implement the OCS Agnus first, and then Denise, Gary, etc., when he's trying to replicate the overall behaviour, NOT, the behaviour of individual chips on the board. He was not concerned by the timings of the signals between the individual ICs on the A500 motherboard.
As for the accuracy of the actual signal timings; I agree that MiniMig's synthesized A500 chip set might be a little off compared to the real thing. This is no big deal in the sense that it is something that can be fixed in a real short window of time. Although I my self have not done any in-depth FPGA programming as of yet, I am certain that it is something that even I could FIX in a matter of hours with a timing diagram of the original A500 handy.
I doubt that someone could fix it in just a few hours. Regardless, if Dennis had the timing info, he could adapt his minimig design to separate into the individual chips if he really wanted to.
Oh, why is it that the signal timing has to be absolutely correct again? Aside from the bugs, MiniMig runs everything A500, doesn't it? It is a true A500 clone after all! Did I actually hear you say "drop-in chip replacements"? Have you any idea what something like that would cost if production is not on an impressive scale? Wouldn't you rather spend your money on a reasonably priced modern implementation of the A500 than on a relatively expensive chip in the hope that none of the other chips need replacing? I know I would.
Jens suggests that by analysing the timings etc at a chip-level he should ultimately end up with a more compact design. Added to that, it helps with debugging the design too. I could see an advantage to being able to use some of the old chips when testing/debugging the design. That way you can see the whole thing work, including inter-chip interactions, before you've finished designing the whole system.
Personally I don't care about the inter-chip timing; I don't have an A500 motherboard; and, seeing as the entire design could fit in one FPGA, that's definitely the way to go for a new product (it sounds like Jens Schoenfeld will be doing that too).
One final note: you seem to have got the idea that I think Dennis' work isn't as good as Jens'. Not at all. I like both projects. I'm very interested in the different approaches thay've taken to ultimately try to achieve the same goal. I'm an electrical engineer and I plan to get back into working with FPGAs at some point, so, looking at these various projects could give me some ideas that will be of use later.
Hans
