@Hans:
Funny, I've been following that thread and I don't recall anything saying that he's been cloning it chip by chip. Sure, he started with the copper coprocessor (which is NOT a chip in it's own right but a sub-component) and then moved to other parts such as the blitter system. That's the only way to do a project like this. I don't have my facts mixed up at all.
It's engineering custom to split a large project up in to manageable subsections in order to maintain a manageable whole. This is also the case when reproducing let's say the A500 to create MiniMig; This is something we both agree upon.
I would like to quote a single sentences posted by Dennis in the "Amiga in FPGA: MiniMig" thread;
Posted on: 2005/12/5 13:46 (This is his very first post!)
"I have been working on this for almost a year now and so far I have the OCS Agnus, Paula, OCS Denise and both the CIA's running in the FPGA." - Here he states the individual chips that he has running in the FPGA. Still sure that you have your facts straight?
Dennis van Weeren has taken an overall behavioural approach. Of course he's implemented each sub-component one-by-one. Just not chip-by-chip. Why would he bother to implement the OCS Agnus first, and then Denise, Gary, etc., when he's trying to replicate the overall behaviour, NOT, the behaviour of individual chips on the board. He was not concerned by the timings of the signals between the individual ICs on the A500 motherboard.
Signal-timings are actually an integral part of the greater whole you call 'overall behaviour' of a microchip. There is no way in hell an FPGA reimplementation of a specific microchip is going to behave anything like the original if the timings are way off. I know for a fact that Dennis has not spent excessive amounts of his development time producing a "cycle exact" copy of the original chip, which is quite frankly the essential difference between MiniMig's synthesized Amiga custom chips and that of Clone-A. Aside from the fact that MiniMig is not a 100% cycle exact reproduction of the A500 (mainly due to the lack of a logic analyzer), there is no way in hell the synthesized chip timings (talking about the inter-chip timings here) are *off* anything more than a slight error percentage as it does actually run Amiga software after all. If I am not mistaken, Dennis has already fixed some bugs that he had due to timing discrepancies.
I doubt that someone could fix it in just a few hours. Regardless, if Dennis had the timing info, he could adapt his minimig design to separate into the individual chips if he really wanted to.
Each and every chip has already been individually defined in this project. As long as D's notes on the source code are clear, anyone that is knowledgeable in Verilog could straighten any timing discrepancies out. The project is going to be released under an open-source licence soon, remember?
Jens suggests that by analysing the timings etc at a chip-level he should ultimately end up with a more compact design. Added to that, it helps with debugging the design too. I could see an advantage to being able to use some of the old chips when testing/debugging the design. That way you can see the whole thing work, including inter-chip interactions, before you've finished designing the whole system.
Jens is WRONG. The size of the design (in verilog, as it doesn't get any smaller than the size of an FPGA and some elementary circuitry outside of that FPGA) is ultimately down to how smart abstract and efficient the programmer can reproduce the functionality of the original hardware. This design-size we speak of is then expressed in number of gates utilized etc. Strictly keeping to an 'exact' cycle accurate design could actually very well involve some overhead concerning the resources utilized within an FPGA AND unnecessarily increase design complexity. What added benefit would more overhead and added complexity have the project may I ask?
Personally I don't care about the inter-chip timing
Neither do I.
seeing as the entire design could fit in one FPGA, that's definitely the way to go for a new product (it sounds like Jens Schoenfeld will be doing that too).
The entire design can already be found in a single FPGA (well, the chip set anyway, next step would be to integrate an 68k or preferably a smaller -in terms of FPGA resources required- equivalent processor, and the disk-controller which Dennis seems to have been too lazy to integrate in the first place). It's called MiniMig. Dennis is actually in the process of developing the first real prototype of the final version (12x12 cm PCB < mini ITX!). I am guessing that if it works like he intends it to, he will call it "final" and release everything to the community (or so I hope!). Yes, that 'Amiga on Chip' does seem to be Herr Schoenfeldt's intention.
One final note: you seem to have got the idea that I think Dennis' work isn't as good as Jens'. Not at all. I like both projects. I'm very interested in the different approaches they've taken to ultimately try to achieve the same goal.
No Hans, I am not under the impression that you think that D's work is any less impressive of that of Schoenfeldt. I am just afraid of the fact that whatever Jens says quite frankly goes, if it's up to some people here... I would like to stimulate people to start their own thought process instead of believing a multitude of what other people say -blindly-.
I'm hoping that he'll answer this question too. Possibly some of the signal timings/characteristics are because of things the original Amiga engineers did in order to keep the chip within the transistor-count budgets of the time. For example, making a signal active low instead of active high could remove a few unneeded gates. That's all I can think of personally.
That would mean that the Clone-A design would not be exactly cycle-accurate anymore but 'within operation limits' like MiniMig.
It's been a pleasure talking to you Hans! You mentioned that you where thinking of getting back in to FPGA development? Will you be participating in the further development of MiniMig when the time comes? :-)
@Donar:
I think Dennis stated that he can not provide us with Hardware for MiniMig, it seems Individual computers can provide hardware for people like me, who are to dumb to create their own 6 layer board with an 75W soldering iron on their wooden workbench.
Actually, I think that Dennis just doesn't want to get into all the hassle paired with the whole mass-production aspect of things and he seems to care about the money involved either, so you are probably right about the fact that Clone-A will provide hardware for the non-technical Amiga users amongst us. We shall see what the future has in store for us.
It is said that the plans for AGA chips are lost, i like the idea that Jens and Oliver at one time, first finishing OCS/ECS will be able to re- implement AGA on real silicon not FPGA. (I think it should be possible if you know all about the inner workings of the chips, right?). I know AGA is old useless technology, bla, bla, nobody needs it in 2006, and real silicon is too expensive either. But I'm a ignorant....so i don't listen.
I happen to know of some hobbyists that are considering to incorporate AGA in to MiniMig as soon as it's source has been released. It aparently isn't too much of a problem. Ah, Shhhssst! Don't ask!
AGA could be re-implemented on real silicon as long as you do have extensive knowledge (could be documented knowledge) on the inner-workings of the chip; no-problem. It can even be done without the extensive knowledge of the inner-workings (reverse engineering), but would just take longer... Still no problem though.
I don't get it. Why would you say that Jens and Oliver would re-implement AGA on silicon instead of FPGA when Jens clearly stated (in the Total Amiga interview) that he'll try to keep his future hardware reconfigurable (FPGA?). What am I overlooking here?
If you think i'm crazy - here is the rest... They could also extend AGA and implement some/all of the features of AAA. Yes i know, as before, to little, to late in 2006. But i'm a believer...
The Amiga still won the last Demo competition in 2006. Even with old crappy AGA and an 68060. So give the old lady a new make up and she'll be ready to win the Demo Competition in 2025 also.
Start learning Verilog and warming up those precious hands of yours! 'Believers' like you are destined to be at the heart of projects like these as a driving force. When the old lady wins the demo competitions in 2025, we all know who to thank. I guess that I'll be buying the beer! :-)
jen-ss (Sander)
