New TerASIC DE0 FPGA board - MiniMIGtg68?

[FrenchShark]

Hi All,

Just released, new Altera based FPGA board from TerASIC:

http://de0.terasic.com/

$119.00 plus shipping.

I ordered one to have a tinker with. Should arrive early next week.

With 15,000 logic units, should be possible to shoehorn a version of Minimitg68 into it

Cheers,
Red

I prefer my MCC board (http://www.arcaderetrogaming.com/2.html): more RAM (16MB), more flash (16MB too), bigger FPGA and the "retro" interfaces already present : DB9 joystick, PS/2, stereo output (the DE0 does not have one !), buffered triple 4-bit dac, SD-Card with 4-bit SD mode.

Regards,

Frederic

[FrenchShark]

I prefer my Replay board
http://www.fpgaarcade.com

more Ram(32MB) more flash (2G SD card) , really big Xilinx FPGA, 2 x db9, 2 x ps2, high quality DAC, buffered and filtered 3x8 bit DAC, SD card with 4 bit SD mode, expansion connector, ARM7 controller and more importantly a supported Minimig port and several other platforms.

Sorry Frederic, I couldn't resist this

Of course yours is better. But it is too expensive, my friend :-).
I am looking for something more affordable.
Concerning the RAM, I have option for 16, 32 or 64MB, I also have a 2GB SD Card and I use FatFS with LFN support.
What Spartan3 size do you have ? 3 millions gates ?
The EP3C25 I am using is equivalent to a 1.5 millions gates Spartan.
Right now, I am coding a Minimig AGA in VHDL, most of the Alice chip with an integrated SDRAM controller is done.
Yaqube's code is actually very useful for this porting.

Regards,

Frederic

[FrenchShark]

But it is not on sale!?


Same goes for you too!

It will be for sale soon.

[FrenchShark]

*alex production run in 2 weeks, you want one?

Price may come down a little with the option of a "lite" board without the large expansion connector, molex power or external input connector.

Frederic, we haven't seen schematics for your board, do you intend to release them?
What about the source code? I assume as you are building on the work of Dennis and Yaqube you will let others do the same?

Anyhow, looks interesting, good luck with it.
Best,
Mike

Our goal is to sell the board at a fraction of the Minimig price.
The price reduction tricks we use are in the schematics. So, I cannot release the schematics yet.
Concerning the source code, it is a 100% rewrite in VHDL. The architecture is different, the bus runs faster and the DMAs are tightly coupled with the SDRAM.
I will release the source code once the board is for sale.

Regards,

Frederic