Motorola 68060 FPGA replacement module (idea)

[billt]

Actually a default model could be to provide just a few instructions and have the rest as trapped instructions. That means one has something workable fast. Then one could make the architecture correct. And then add the full instruction set.

If one start with the instructions and then try to impose the correct architecture.. well it could be messy

That's a big part of why "they" moved away from hardwired control units in favor of microcoded control units. My own education thus far was about hardwired style, which is very dependent on the instruction set. I was hopin gto take the advanced followup course now, but it wasn't on the schedule. I'm trying to go through the Coursera one now, which is pretty advanced. Not sure if they explain microcoding or if that assumes you already know it. Going to try and find some time to read up on it more regardless.

[billt]

Regarding instruction set (ISA) I was thinking in general why they changed it. Because the end result is a slight confusion.

where was that? I seem to have missed it.

[billt]

For those saying that Altera is the better fpga for this task, what exactly makes it better, and what are you comparing it to on the Xilinx side?

[billt]

The following instructions wouldn't be in the pipeline yet, at the point you make the prediction, that's the whole point, to avoid having to flush the pipeline when you get to the branch.

What exactly happens when you have to flush? I imagine it being a mux at the opcode register at each stage of the pipeline, and if that stage gets flushed then flip the mux to bring in a nop rather than the opcode from the previous stage on the next clock edge. Then as this now-a-NOP propogates down the pipeline, whatever other things are on other stage control regs such as register file addresses, ALU input selects, bypass opportunities, etc. just get ignored. I don't think the flush really needs to be particularly time consuming. yea, those NOPs need to propogate out, but that's really more an observation of new instructions propogating in, and that's going to happen either way.

Or are there better ways of doing this?

I wonder if you understood my idea properly, so I'll try explaining it again. The instruction stream is read into a FIFO (which I believe is a fairly normal thing to do) and as soon as a test followed by a branch is read in, it can do the test immediately (which is a very simple operation) and predict the branch based on that. So as long as the register doesn't change by the time the branch instruction comes out of the other end of the FIFO the branch will have been predicted correctly.

The test may not always be able to be done immediately. Might it not depend on the writeback of an instruction ahead of it but still in the pipeline and not yet finished? You may not yet have the right thing there to test just yet. Such as decrementing a loop counter might be right ahead of the test for 0...

[billt]

Do we care so much about the size of the core anyway? If the aim of the game is the fastest 68k CPU, the fastest rated FPGAs tend to be quite big anyway. Unless we're squeezed for space I wouldn't worry about it.

For this particular thread topic, probably we do not care as much about core size. But as some potential softcore CPU designs overlap into other project boundaries, there are other reasons to make a very small softcore. Then anyone working on this thread's topic can choose to try that out or not.

Anyway, one big step in our thread is hardware. A PCB with an FPGA on it. That is a big hurdle to any other detail. I've started an open PCB design at upverter, but have not progressed to any meaningful degree. I also have a related project at github, partially for any HDL that may be tried, and partially to hold Eagle design files since upverter did not yet support BGA footprints. (I believe it does now)

Anyone can join in, but don't wait for me to finish anything. My track record for completion is not too great. Never enough time, and I have one project far more important to me than even this one... And of course feel free to do N more independent projects. Hopefully at least one will have something to plug in someday.

http://upverter.com/amigabill/215b379ff943fc80/FP68060/

https://github.com/amigabill/fp68060

[billt]

On another note... I just found a source in China with the Rev 006 MC68060RC50 chips.  They apparently have over 10,000 of them left over from a production run of call center boards.  I have a couple of samples coming.

Let us know what they actually are after some testing. Hopefully they don't give you a couple rare real ones for samples to get you into a big buy of fake ones... If this turns out legit, you could end up being a supplier to a lot of desperate Amiga fans.

As this is a highly counterfeited part (the 06 version in particular), don't believe the writing on the package. That's easily changed. See if you can set up a test rig like how mikej checks them, and have the guts of the chip tell you what it actually is. it seems odd that such a large pile of them are sitting around somewhere when people are having such a terrible time getting them.

[billt]

Hi,

What speed is your laptop, and who makes it?  (stupid question probably Apple)

smerf

Dell Latitude e6530 i7-3720QM @ 2.60 GHz + 8GB ram and Nvidia NVS-5200M graphics is my own. It's for school (master degree in electrical/computer engineering stuff), as well as my personal cad station for Eagle, Kicad, Xilinx, Altera, etc. for projects like this topic. I'd be interested in AROS in a VM or in a Wubi-alike install on this thing too, but haven' thad time to investigate yet.

Lenovo Thinkpad T530 i5-3320M @ 2.60GHz + 8GB RAM + NVS5400M graphics is my work-supplied one. ASIC EDA terminal into the cloud.

iBook 14inch G4 @ 1.42GHz + 1.5GB ram is not really used, I'm hoping for MOS support at some point. Needs new backlight or LCD panel. The LCD is displaying the picture, but it's completely dark so I can't actually see it. Works great on an external monitor.

And, finally, my most charming of all, the OS4 laptop is, well, unfortunately, nothing more than a bit of sarcasm at the time of my post there. Should the mythical netbook or anything bigger/faster ever materialize, I'll buy one.

Anyway, back to topic...