JetRacer wrote:
Lando: I don't think there's a single accurate statement in your post.
Hang on, isn't the guy (Lando) actually working on developing stuff for PS2? Ok, so maybe not the PS1 but I think he aught to know his stuff. If he says PS2 is no big deal compared to A1 then it's not a great leap of intuition to say that the PS1 isnt :-)
I've programmed on MIPS, 68K and PPC. The R3000 is no big deal, believe me. True, it's a pipelined architecture that breaks instructions into stages. That's nothing special. Even the 68030 does that ;-)
Simplifying slightly..
First instruction is fetched. It's passed to the execution unit, the fetcher is immediately free again to get the second.
The execution unit passes the result of the first to the retirement stage, the execution unit is immediately free to process the second instruction.
etc...
So, an instruciton passing through X stages, at say one cycle per stage can achieve an overall throughput of one instruction/cycle.
That's pretty much all there is to pipelining.
If you have several execution units you can achieve an overall throughput of several instructions per cycle, the exact number depending on the dependencies between adjacent instructions.
This is not unique to MIPS, most RISC (and even CISC, eg 68060) processors do this.
For example, a PPC 603e can retire 3 instructions per cycle and have up to 5 in execution at any given moment.
A G3 600 outperforms your basic MIPS R3000 / 33 by a silly amount...
