Double check a few things first. I reconstructed this modification mostly from memory without an actual rev 6A in front of me. I found the photo that I cropped and modified on line, along with schematics. When I did this years ago, I carefully verified actual connections. I'm pretty sure I'm right, but cannot guarantee it.
Verify that the top right pad of the 2x4 pads goes to pin 35 of Agnus and the top left goes to pin 48 of the 68000 (Address A20). Pin 35 is the external clock for the "A" version, but A20 for the "B" version. It's hard to read the online schematic I found, but Agnus pin 56(?) is the /RAS1 for the 2 bank memory, 8 256k x 4 chips for 1 meg, and /RAS1 isn't used for just 1 bank of 4 chips. /RAS0 is. With the (B) Agnus, it is DRAM address 9 (DRA9). This should go to pin 2 of U35 if I read the schematic right.
You see, you can simply add four 256k x 4 memory to it and have 1 meg chip memory. Only /RAS0 is needed for 1 bank.
The 2x2 jumper changes should reroute /RAS0 (after latching though the 74F244 U35, pin 15 to 5) from the occupied bank of 256kx4 pin 4 to the unoccupied bank pin 4 where the 1 meg x 4 will be placed. What was /RAS1 (8372A) is A20 (8372B), latches through the 74F244 U35, 2 to 18, rerouted to pin 5 of U16 to U23. In the first bank, U16 to U19, pin 4 and 5 are connected, so the 1meg x 4 memory cannot be used there. The 256k x 4 memory chips pin 5 is NC, but A9 for the 1 meg x 4.
A500 rev 6a and rev 7 schematicJDEC memory pinout goto PDF page 77
A500 board photos
