Given the very simple way Akiko works (write chunky words to its registers and then read back/copy the planar converted data) it's no surprise the speed up is rather moderate. AFAIR there was some space left on the gate array that was to become Akiko and the developers tried to think up something useful. Well, they did, given the budget.
Something that would really have made a change:
- adding a c2p converter in front of Lisa's bus interface with on-the-fly conversion - no waste of bandwidth here
or better:
- adding a chunky mode to Lisa - was missing from AGA from the start
If I understand this correctly, Akiko was the C2P equivalent of the FPU? Given that, I have a bitter taste over the Akiko. I would have thought you could have it actually operate on a segment of memory if it was going to be a grafted-on component. My thought was double- or triple-buffer (if the 2MB memory permitted), sick Akiko on the off-screen buffer, then switch.
Better to be integrated, as you say, in the existing custom chipset. Very sad, indeed.
