FPGA for dummies

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We are now scanning dies of some 1980 ASICs. From this, we can do polygon extraction - then transistor extraction and then reduce to gates.

Amiga ASICs ?

Scanning electron microscope or high-resolution camera?

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I consider emulation when the underlying layer has to use clock cycles to propagate state translations from the guest hardware to the real hardware API.

Regarding the Meta-FPGA, it's an interesting project because it eliminates the vendor-lock-in of synthesation software. In fact one could order a basic FPGA ASIC with plain fabric if enough money could collected to cover startup costs. Every extra chips is as expensive as a postage stamp..

@billt, url of that 404-site?

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Papper is just emulation of real writing..

I thought the Amiga team used SAGE computers (aka "Agony") ..?

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That's not a requirement of an FPGA implementation.You can do truely combinational logic in an FPGA, select the final mux to pass the non-flipflopped signal instead of the flipflopped signal. No flipflop, no clock. Only passgates, multiplexers, and buffers, and none of those need a clock to be present for them to work. None of them even have clock pins to connect one to.

If your own circuit is a sequential thing, such as a state machine, then you will need to use flipflops to implement that, same as you need to do in a custom ASIC. You can't do sequential without a clock. And the clock involved in the FPGA here is the one for your own circuit design, not some FPGA "background" clock. There is no FPGA "background" clock driving the FPGA silicon to act like your own circuit.

I'm talking about translating between hardware environments by means of cycling through translation stages. Which in most cases is implemented by means of software.

MPGA - Meta Programmable Gate Array, version 0 brought back

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My toaster is conspiring against me!

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Either the logic circuit meets the timing specification or it doesn't ..!

How you accomplish that is irrelevant.

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One  of the methods can adhere to the timing specification of the original design.

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I did say one of the methods, I didn't say the other didn't. You assumed.
A processor unless given an uneconomical performance will have a low probability to adhere to the clock cycle timing of the orignal design.

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Machines that adhere to the same electrical specification as the "original" is real.

The missing masks, and original code just shows how bad proprietary designs are for long term usage. But that's the way it is, like it or not. Someone could scan the orignal chips (don't throw them!). But such process is still hard. So the method that remains is reverse engineering.

Does anyone know how the orignal designs were managed?, I know 6502 was done with manual methods like pen and papper, OCS used logic chips and wire-wrap. But somewhere after that they ought to migrated into some electronic design system.

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All seems to indicate that decay of cells happen with an exponential rate (linked to capacitor discharge curve vs internal noise, I guess).

Likely related to the threeshold of the internal sense amplifiers. Ie before it reaches the thermal noise floor.

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One could exploit FPGA "floor planning" to accomplish some performance gains. On ASIC I guess it's all about floor planning..

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Holy crap, all my AMD are emulating Intel

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Is there any preference for nMOS or pMOS in regards to stability and noise immunity, or even propagation delay?

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At least I know FreeBSD or Linux works better. But any multitasking especially non-realtime OS is going to produce a less responsive experience.

However an FPGA can produce accurate timing to most system components.

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The question is to ask:

Will it be more accurate?

What is the most sucessful way to do MFM decoding or that matter GCR from disc?
 * Write it in BASIC using INB .. on a single user system?
 * Write it in C using inb() on a multiuser system?
 * Write it in assemble using inb xx on a bare bones system?
 * Code it as an hardware description (HDL) equalient ?
 * Wirewrap it with 7400 circuits?
 * Etch an ASIC at horrendous cost?

Recall that these signals come at a synchronous specific time and doesn't wait for anything. And you need to listen to them with precision and act on them on time, all the time. There's also DRAM signals, bus responses, video generation, communication etc that all need the right response on time.
Add the complexity of several way more complicated circuits that all act in parallel with defined realtime responses. If you try to implement this on a single CPU system you will need to find out which signals that need hard realtime response and do a check-and respond to all those signals without ever delaying outside time boundaries. This means system response will be dependent on the total service loop execution time. A huge liability. The other liability  is that this signal servicing will not be in lock step with the system as a whole and thus introduce time jitter..
(a multi-CPU system makes this easier, but it still suffer from the same fundamental flaw)

When the possibility exist to model a signal system which is what the electrical circuitry really implement. The design thought process can focus on the modeling instead of explicit response times and time critical signal hooks. And when the model is correct it will "just work(tm)". Instead of having to figure out how to implement this as sequential code. So it is in the essence signal path description vs sequential code equalient.

As bonus that comes from being unimpeded by central clock phase, cache, logic bare bone etc one can interact with real hardware interfaces. A PC with a 2 GHz CPU should be able to respond to an I/O within 3 instructions so in the ballpark of 1.5 ns. But real life test rarely finds the parallel port respond faster than 1000 ns.

I hope this gives some understanding on the issues that FPGA/CPLD/7400 etc makes it possible to deal with efficiently.

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I guess some games/demos just won't be themself in an environment that lack signal precision.