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Author Topic: TG68 - The Open Source Minimig CPU into the FPGA  (Read 22298 times)

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Offline TobiFlexTopic starter

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TG68 - The Open Source Minimig CPU into the FPGA
« on: November 26, 2007, 12:49:53 PM »
Today I have publish my 68K CPU Core:

Open Source 68000 IP Core

Viele Grüße
TobiFlex
 

Offline TobiFlexTopic starter

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Re: TG68 - The Open Source Minimig CPU into the FPGA
« Reply #1 on: November 26, 2007, 01:15:30 PM »
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Do you think it would be hard to add 68020 support?


Yes!
But for now we can clock the CPU faster. The CPU Kernal is very fast and only the bus wrapper make it slow.
The Kernal is 2x-3x faster then the 68000 with the same clock and you can clock them with 28MHz.
I think it is possible to make the minimig 8x-12x faster then the original.

Viele Grüße
TobiFlex
 

Offline TobiFlexTopic starter

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Re: TG68 - The Open Source Minimig CPU into the FPGA
« Reply #2 on: November 26, 2007, 02:54:12 PM »
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Is there any attempt to make the instruction timings the same as the original 68k?


most of the byte and word instructions are exact. Long and mulu/divu/rotation instructions are faster. But - Hehe - this is version 1.0!

Viele Grüße
TobiFlex
 

Offline TobiFlexTopic starter

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Re: TG68 - The Open Source Minimig CPU into the FPGA
« Reply #3 on: November 26, 2007, 05:57:23 PM »
Into the first link I can read this:
Quote
Much of my testing was conducted on the MC68EC000 processor


The MC68EC000 is different from the 68000. I have my Core let run against a real MC68HC000 and can not find software differences when the Kickstart or some programms are running. So I know all importand Instructions works correct. About never used Instructions I can not say anything.
Example: I have found no program for the AMIGA that use CHK or MOVEP Instructions.

About the doc on the second link. My Core use no prefetch. My Core use classical Fetch/Execute last - Decode - Fetch next/Execute - order.
Thats why most Instrucions can execute in 2 clocks. The Bus wrapper expand this to 4 clocks.
But for the minimig is the prefetch not so important. The core is fast enough to decode the opcode between as=high. So the timing is the same as the 68000 timing.

On my DE2 Board with a real MC68EC000 and running ANARCHY1 DEMO I can see some rendering error but with the softcore I can not.
I dont know what happens but I think my core has a high Betatested Level. (Upss I hope you can understood my - sorry for my poor english)

Viele Grüße
TobiFlex
 

Offline TobiFlexTopic starter

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Re: TG68 - The Open Source Minimig CPU into the FPGA
« Reply #4 on: November 26, 2007, 06:39:30 PM »
Quote

Try this program

http://amiga.nvg.org/warlock/adf/b/Birk+Sundell/100C64Tunes.adf.gz


Ha! OPCODE 0x0F0E MOVEP.W .....
My Validator stop here.

Thank You Alexh. Now I can Implement the Movep Instruction.

Do you know a .ADF Source from the hardwired demo?
 

Offline TobiFlexTopic starter

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Re: TG68 - The Open Source Minimig CPU into the FPGA
« Reply #5 on: November 26, 2007, 06:47:09 PM »
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Excellent news!!

This opens up some whole new possibilities...
(pondering about Minimig rev2.0  )


I'm also on the bridge, Captain. ;-)
 

Offline TobiFlexTopic starter

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Re: TG68 - The Open Source Minimig CPU into the FPGA
« Reply #6 on: November 26, 2007, 07:03:11 PM »
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I need a bigger FPGA


DE1 Board?  ;-)
 

Offline TobiFlexTopic starter

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Re: TG68 - The Open Source Minimig CPU into the FPGA
« Reply #7 on: November 26, 2007, 08:18:59 PM »
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Ok, I just looked it up. Is this the correct board?

http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=83


Yes thats right. This is the same Board as this:
http://www.altera.com/products/devkits/altera/kit-cyc2-2C20N.html
 

Offline TobiFlexTopic starter

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Re: TG68 - The Open Source Minimig CPU into the FPGA
« Reply #8 on: November 26, 2007, 10:19:13 PM »
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Do you have a DE-1 to port it to?

Yes i have it done. But I am not satisfied yet.
I think i have a bug into the Floppycontroller.
If I have fix it I will release all the Source Code to.
 

Offline TobiFlexTopic starter

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Re: TG68 - The Open Source Minimig CPU into the FPGA
« Reply #9 on: November 28, 2007, 07:27:30 AM »
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I wonder if Dennis and Tobias have looked at it?


Yes I have. But I can not seen a advantage.
The other point: I love Quartus - The Altera FPGA Design Software - especial the integrated Logic Analyser "SignalTap II". He is also included into the Web Edition. I have found many Bugs with the help of "SignalTap II".


   
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@ ChaosLord
Is your fpga 680x0 using a barrel shifter for shifts and rotates?

Use a real 68000 a barrel shifter?
NO!
So I also not use a barrel shifter in my Core.

Quote

@alexh
I am sure TobiFlex could get the size of the TG68 down abit with some good constraints and if he made some of the instructions multi-cycle.


I will not optimize the size next time.
I will only optimize the function and speed next time and I think I need more LCs for the optimized Design.
 

Offline TobiFlexTopic starter

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Re: TG68 - The Open Source Minimig CPU into the FPGA
« Reply #10 on: November 28, 2007, 09:51:39 AM »
I should use a "one hot State Machine" for the signal "microaddr". This could bee an effect.
 

Offline TobiFlexTopic starter

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Re: TG68 - The Open Source Minimig CPU into the FPGA
« Reply #11 on: November 28, 2007, 02:12:40 PM »
Hi,
The first update for the TG68 Core:

Open Source 68000 IP Core

I have added the MOVEP Instruction and found a Bug in MOVEQ. If MOVEQ was interrupted the data never stored into the Register.
Now is the Floppy Emu also stable. It was the CPU Core Bug!
Now I can compile stable versions for the DE1 and DE2 Board :-)

The CHK Instruction is not so difficult - but I must make some changes into the Trap system  and this IS difficult :-(
 

Offline TobiFlexTopic starter

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Re: TG68 - The Open Source Minimig CPU into the FPGA
« Reply #12 on: December 04, 2007, 05:18:12 AM »
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eslapion wrote:
The aforementioned board has bits numebered 0 to 2 on these 3 channels. 0 to 2 means 3 bits per channel 3x3=9 bits per pixel on the final output. and 2^9=512

Thats not true! That was the color count for the XESS Board.
The DE1-Board use 4 Bits per Color = 3x4=12 bits per pixel and 2^12=4096. The DE1 Board has the same color count as the minimig!
The DE2-Board use 10 Bits per Color = 3x10=30 bits per pixel!
Viele Grüße
TobiFlex
 

Offline TobiFlexTopic starter

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Re: TG68 - The Open Source Minimig CPU into the FPGA
« Reply #13 on: December 04, 2007, 07:57:57 PM »
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eslapion wrote:
What really gets my attention with the Xess board is that it is said to be able to carry up to 1Million gates. The DE2's cyclon II is said to be limited to around 68000 (hey nice number...) logic elements.


You can't compare Gates with logic elements. On the xilinx webside i found this:
XC3S1000 = 17280 LC's
XC3S1200E= 19512 LC's
On Alteras Webside I found this:
EP2C20 = 18752 LC's (the DE1 Board chip)
EP2C35 = 33216 LC's (the DE2 Board chip)
The Minimig Core on the the DE1 Board use 13708/18752 = 73% of the Logic elements. It include Dennis Minimig Core, my TG68 Core and my Spihost with Z80 Core.
The complet Core will fit into all this chips.


Quote
Minimorph wrote:
Is this an Altera DE1 :-

http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail?name=544-1736-ND

Yes it is the DE1 Board!

Quote
Belial6 wrote:
If there is any testing I could do, and I could get the bitstream (?) files from you, let me know, and I will get a DE-1.

You can test Games and applikationen. If you like I send you the Bitstreamfiles.

Viele Grüße
TobiFlex
 

Offline TobiFlexTopic starter

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Re: TG68 - The Open Source Minimig CPU into the FPGA
« Reply #14 on: December 04, 2007, 09:40:25 PM »
Quote

MskoDestny wrote:
Out of curiousity, what's the "Spihost with Z80 Core" used for?


All what the PIC18 do on the Minmig do the DE1 with my spihost except the FPGA Config. I have take Dennis C-Code for the PIC and have it adapted for SDCC and the Z80.
So you don't need a PIC anymore.