Current FPGA tech (that is, chips that are affordable enough to use in projects like this) does not really allow a MMU, because it would slow the CPU design down too much to be acceptable
As long as the address is in the translation cache then an mmu doesn't slow the cpu down. Unless you're really short on space in the fpga then it's just a choice of whether you want to support it or not.
IMO MMU is important enough that natami should support it.
