Well, let's go into detail here, if you'd like Jose:
roughly 2.5 million transistors total for the design as/is. Design done in a HDL called "M", no longer in major use it seems. However, Mentor has conversion tools to render these to Verilog in short order, so $120k for the tools needed.
now, 2.5 million transistors comes down to roughly 500k gates, depending on register handling, any SRAM included, etc, so 500k is a good estimate. half of the gates are in 1 chip, Andrew. The other half are split among the remaining 3 chips. Now, need to double 2 of the chips, to get the 64-bit configuration.
So, we need a single 250k gate FPGA's and 5 50k gate FPGA's.
Altera has several FPGA's that fit the bill. For the 5 smaller ones, I'd recommend Flex10k's. For Andrea, use an Apex20KC, and throw in a DDR-RAM or sDRAM controller to replace the legacy model as well as a PCI bridge over the off-chip logic that's there now, effectively for free.
Total cost for the chips in bulk: $18.