Another one of my hare-brained schemes has been ill-conceived and is on its way.
Felt like learning more about how the DRAM sub-system works on the Amiga, so I've set off to create a new redesigned A501 512K memory module for the Amiga 500's.
I'm documenting all of the DRAM timing of the RAS/CAS's/Write Enable/68K latches because I don't think it's been done before. And I don't see it in any of the official documentation.
So I'm starting to put up Logic Analyzer traces that have all the important details.
I'm using about USD $2.50 worth of glue logic parts, and < $5 memory SRAM chip.(SRAM?!@# the horror). The 56-pin header connector is one of the expensive parts, around $4.
The glue logic to convert DRAM RAS/CAS -> Chip Enable works in simulation, testing in hardware is forthcoming....
Project detailed at
http://www.techtravels.org/amiga/amigablog/?page_id=942with blog posts at
http://www.techtravels.org/amiga/amigablog/?cat=28Everything is open-source/open-hardware.
Constructive comments always appreciated.
Thanks
kamiga